H3LIS100DL datasheet(32/38 Pages) STMICROELECTRONICS

32 / 38 page

H3LIS100DL

32/38

DocID027504 Rev 2

7.14

INT1_SRC (31h)

Interrupt 1 source register. Read-only register.

Reading at this address clears the INT1_SRC IA bit (and the interrupt signal on the INT 1

pin) and allows the refresh of data in the INT1_SRC register if the latched option is chosen.

7.15

INT1_THS (32h)

7.16

INT1_DURATION (33h)

Table 40. INT1_SRC register

YHYL

XHXL

Table 41. INT1_SRC description

Interrupt active. Default value: 0

(0: no interrupt has been generated; 1: one or more interrupts have been generated)

Z high. Default value: 0

(0: no interrupt, 1: Z high event has occurred)

Z low. Default value: 0

(0: no interrupt; 1: Z low event has occurred)

Y high. Default value: 0

(0: no interrupt, 1: Y high event has occurred)

Y low. Default value: 0

(0: no interrupt, 1: Y low event has occurred)

X high. Default value: 0

(0: no interrupt, 1: X high event has occurred)

X low. Default value: 0

(0: no interrupt, 1: X low event has occurred)

Table 42. INT1_THS register

THS6

THS5

THS4

THS3

THS2

THS1

THS0

Table 43. INT1_THS description

THS6 - THS0

Interrupt 1 threshold. Default value: 000 0000

Table 44. INT1_DURATION register

D6D5D4D3D2D1D0

H3LIS100DL Datasheet(PDF) 32 Page - STMicroelectronics

H3LIS100DL Datasheet(HTML) 32 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL