Philips Semiconductors

Product data

PCKV857A

100-250 MHz differential 1:10 clock driver

2003 Jul 31

6

AC CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

WAVEFORM

CONDITION

MIN

TYP

MAX

UNIT

Static phase offset

Figure 1

-350

0

350

ps

Output clock skew

Figure 2

—

—

150

ps

Output clock slew rate

Figure 3

1

—

2

V/ns

Jitter (period)

Figure 4

-75

—

75

ps

Jitter (cycle-to-cycle)

Figure 5

-75

—

75

ps

Half-period jitter

Figure 6

-75

—

75

ps

LOW to HIGH level

propagation delay

Test mode/CLK to any

output

—

3.7

—

ns

HIGH to LOW level

propagation delay

Test mode/CLK to any

output

—

3.7

—

ns

NOTE:

1. Refers to transition of noninverting output.

The PLL clock distribution device and SSTL registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation

SW00945

SSTL16877

or

SSTV16857

PCKV857A

FRONT SIDE

SSTL16877

or

SSTV16857