PC97307VUL datasheet(61/218 Pages) NSC

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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)

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4.5.2

APC Control Register 2 (APCR2), Index 41h

FIGURE 4-12. APCR2 Register Bitmap

Bit 0 - Timer Match Enable (TME)

0 - Pre-determined date or time event is ignored.

1 - Match between the RTC and the pre-determined

date and time activates the ONCTL output signal.

See MOAP (bit 4) of APCR1 for an overriding case.

Bit 1 - RING Source Select (RSS)

0 - RING source is RING/XDCS signal, regardless of

X-bus Data Buffer (XDB) select bit of SuperI/O

Conﬁguration 1 register.

1 - RING source is GPIO23/RING signal.

Bit 2 - RING Pulse or Train Detection Mode (RPTDM)

0 - Detection of RING pulse falling edge.

1 - Detection of RING pulse train above 16 Hz for 0.19

sec.

Bit 3 - RING Enable (RE)

0 - RING input signal is ignored.

1 - RING detection activates the ONCTL output signal,

unless it is overridden by the MOAP bit, bit 4 of the

APCR1 register.

Bit 4 - RI1 Enable (R1E)

0 - RI1 input signal is ignored.

1 - A high to low transition on the RI1 input pin acti-

vates the ONCTL output pin.

See MOAP (bit 4) of APCR1 for an overriding case.

Bit 5 - RI2 Enable (R2E)

0 - RI2 input signal is ignored.

1 - A high to low transition on the RI2 input pin acti-

vates the ONCTL output pin.

See MOAP (bit 4) of APCR1 for an overriding case.

Bit 6 - Switch Off Delay Enable (SODE)

0 - ONCTL output pin is deactivated immediately after

the Switch Off event.

1 - After the Switch Off Event, ONCTL output signal is

deactivated after a 5 or 21 second Switch Off delay.

Bit 7 - Reserved

This bit is reserved.

RPTDM

R1E

R2E

SODE

Reserved

76543210

TME

RSS

Index 41h

Power-Up

Required

APC Control

(APCR2)

Reset

4.5.3

APC Status Register (APSR), Index 42h

Bits 5-0 in this register are cleared to 0, when this register

is read.

FIGURE 4-13. APSR Register Bitmap

Bit 0 - Timer Match Detect (TMD)

This bit is set to 1 when the RTC reaches the pre-deter-

mined date, regardless of the Timer Match Enable bit

(bit 0 of APCR2). After first Power-Up, the RTC and the

pre-determined date, are 0 and so this bit is set. It is rec-

ommended to clear this bit by reading this register after

first Power-Up.

Bit 1 - RING Detect (RID)

This bit is set to 1 when a high to low transition is detect-

ed on the RING input pin and bit 2 of APCR2 is 0, or

when a RING pulse train is detected on the RING input

pin and bit 2 of APCR2 is 1, regardless of the status of

the RING enable bit.

Bit 2 - RI1 Detect

This bit is set to 1 when a high to low transition is detect-

ed on the RI1 input signal, regardless of the RI1 Enable

bit.

Bit 3 - RI2 Detect

This bit is set to 1 when a high to low transition is detect-

ed on the RI2 input pin, regardless of the RI2 Enable bit.

Bit 4 - Fail-Safe Timer Detect (FTD)

This bit is set to 1 when the Fail-safe timer reaches ter-

minal count.

Bit 5 - Switch Off Event Detect (SOED)

This bit is set to 1 when a Switch Off event is detected,

regardless of the Switch Off Delay Enable bit.

Bit 6 - Reserved

Reserved.

Bit 7 - RING Status Bit (RS)

Holds the instantaneous value of the selected RING pin.

RI1 Detect

FTD

SOED

Reserved

76543210

TMD

RID

RI2 Detect

Index 42h

Power-Up

Required

APC Status

(APSR)

Reset

PC97307VUL Datasheet(PDF) 61 Page - National Semiconductor (TI)

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