PC87570-ICCSLASHVUL datasheet(50/168 Pages) NSC

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Host Bus Interface (HBI)

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5.4.2

Wake-Up from Host

When required, the host can switch the PC87570 to Active

mode using the host interface ports. To wake-up the

PC8570 to Active mode when the host accesses shared

memory, configure the MIWU to enable shared memory

wake-up inputs.

5.4.3

Host Power-on Indication

The input signals to PC87570 from the host bus are validat-

ed by the HPWRON input. The application should connect

HPWRON pin to a circuit that guarantees that the signal be-

comes high only after the chipset (i.e., the device that drives

the host bus controls) supply is stable. Also, it should be-

come low before the chipset supply becomes unstable.

5.5

HOST ACCESS TO PC87570 RESIDENT I/O DEVICES

The PC87570 has three resident I/O devices: the KBC, the

PM, and the RTC/APC channels. An additional channel is

used for configuration (see Table 5-1. The host should use

the HAEN, HIOR and HIOW signals to access the resident

I/O devices.

5.5.1

Host Access to Configuration Registers

The host interface to the PC87570 I/O devices is controlled

by the host configuration mechanism. This mechanism de-

termines which device can be accessed and at which ad-

dress. On reset, the legacy addresses are selected, and the

devices may be enabled or disabled, depending on the

HDEN strap input.

The CR16A firmware can define an additional address for

the motherboard PnP sequence. This address must be de-

fined before the host starts to access the PC87570. To de-

fine the address, the CR16A application code should

program accordingly the HCFGBAH and HCFGBAL Regis-

ters, and set VHCFGA bit in the CST2 Register to validate

the new address. The HCFGBAH and HCFGBAL Registers

and VHCFGA can be locked (made read only) by setting

HCFGLK bit in the CST2 Register. This bit is cleared during

power-up and WATCHDOG reset. Once HCFGLK is set,

the firmware cannot clear it.

5.5.2

Host Access to Resident I/O Devices

The host accesses the three legacy devices at the addresses

defined in Table 5-1. (These addresses refer to host I/O

space.) Since these devices are typically handled by the sys-

tem BIOS, the default addresses are identical with the ad-

dresses of the legacy devices, and should not be altered.

However, for special applications, I/O address mapping can

be changed by reprogramming the internal chip select regis-

ters as detailed in Table 5-4. For simplicity, this document re-

fers to the legacy addresses.

The PC87570 decodes the host interface 64 Kbyte I/O

space using HA0-15 to identify the address of any one of

the three devices and the configuration registers. When an

access to a device address is identified and the device is

enabled, an internal chip select signal is generated.

In addition to the chip select signal, the PC87570 uses HA0

to distinguish between the two RTC/APC registers, and

HA2 to distinguish between the two registers of the KBC

and PM ports.

Table 5-1. Host Interface Registers

5.5.3

Host Bus I/O Cycles

The bus cycle and its detailed timing are described in Fig-

ures 19-16 on page 150 and 19-17 on page 151.

5.6

KBC CHANNEL

The host interface of the PC87570 is compatible with the

legacy 8042 host interface. It is based on two registers:

Command/Status and Data. The host interface logic gener-

ates interrupts to the host and CR16A according to the sta-

tus of the input and output data buffers. Figure 5-2 provides

a schematic description of the host interface KBC channel.

The KBC channel hardware consists of three registers:

Status Register, which can be read by both the

CR16A and the host, and written to by the CR16A

Data Out (DBBOUT) Register, which can be written to

by the CR16A and read by the host

Data In (DBBIN) Register, which can be written to by

the host and read by the CR16A

5.6.1

Status Register

The status of the KBC data buffers can be read by both the

host and the CR16A. Bits 2 and 4-7 can be written to by the

CR16A. Bits 0, 1 and 3 are controlled by the hardware to in-

dicate the DBBIN and DBBOUT registers status. The host

should read address 64h to obtain the contents of the Status

to access the same information. The format of the Status

Section 5.12.8).

Channel

Default

Legacy

Address

Type Description

Host

Conﬁgura-

tion

See

Section

5.13

R/W

INDEX

R/W

DATA

Keyboard

and

Mouse

0060h

Data

DBBOUT

Data

DBBIN

0064h

Status

STATUS

Command

DBBIN

Power

Manage-

ment

0062h

Data

DBBOUT

Data

DBBIN

0066h

Status

STATUS

Command

DBBIN

RTC

and

APC

0070h

R/W

Index

INDEX

0071h

R/W

Data

DATA

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