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TNETV1647GSTZWT Datasheet(PDF) 223 Page - Texas Instruments |
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TNETV1647GSTZWT Datasheet(HTML) 223 Page - Texas Instruments |
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223 / 236 page ![]() VLYNQ_CLK VLYNQ_TXD[3:0] VLYNQ_RXD[3:0] 1 2 3 4 Data Data TMS320DM6441 www.ti.com SPRS359E – SEPTEMBER 2006 – REVISED AUGUST 2010 Table 6-107. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for the VLYNQ Module (see Figure 6-75) 1.05 V and 1.2 V NO. PARAMETER UNIT MIN MAX Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid 1 ns [SLOW Mode] 1 td(VCLKH-TXDI) Delay time, VLYNQ_CLK high to VLYNQ_ TXD[3:0] invalid 0.5 ns [FAST Mode] 2 td(VCLKH-TXDV) Delay time, VLYNQ_CLK to VLYNQ_TXD[3:0] valid 9.75 ns Table 6-108. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-75) 1.05 V 1.2 V NO. UNIT MIN MAX MIN MAX RTM disabled, RTM sample 1.1 0.8 ns = 3 RTM enabled, RXD Flop = 0 2.8 2.2 ns RTM enabled, RXD Flop = 1 2.5 1.9 ns RTM enabled, RXD Flop = 2 1.8 1.4 ns Setup time, VLYNQ_RXD[3:0] 3 tsu(RXDV-VCLKH) valid before VLYNQ_CLK high RTM enabled, RXD Flop = 3 1.1 0.8 ns RTM enabled, RXD Flop = 4 0.4 0.4 ns RTM enabled, RXD Flop = 5 0 0.1 ns RTM enabled, RXD Flop = 6 -0.3 -0.2 ns RTM enabled, RXD Flop = 7 -0.5 -0.4 ns RTM disabled, RTM sample 2 2 ns = 3 RTM enabled, RXD Flop = 0 0.6 0.6 ns RTM enabled, RXD Flop = 1 1 1.0 ns RTM enabled, RXD Flop = 2 1.5 1.5 ns Hold time, VLYNQ_RXD[3:0] valid 4 th(VCLKH-RXDV) after VLYNQ_CLK high RTM enabled, RXD Flop = 3 2 2.0 ns RTM enabled, RXD Flop = 4 2.5 2.5 ns RTM enabled, RXD Flop = 5 3 3.0 ns RTM enabled, RXD Flop = 6 3.6 3.5 ns RTM enabled, RXD Flop = 7 4.1 4.0 ns Figure 6-75. VLYNQ Transmit/Receive Timing Copyright © 2006–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 223 Submit Documentation Feedback Product Folder Link(s): TMS320DM6441 |
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