SPC563M64L7 datasheet(34/48 Pages) STMICROELECTRONICS

34 / 48 page

Device overview

SPC563Mxx

34/48

Doc ID 13850 Rev 6

The DSPI supports these SPI features:

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Full-duplex, synchronous transfers

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Selectable LVDS Pads working at 40 MHz for SOUT and SCK pins

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Master and Slave Mode

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Buffered transmit operation using the TX FIFO with parameterized depth of 4 entries

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Buffered receive operation using the RX FIFO with parameterized depth of 4 entries

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TX and RX FIFOs can be disabled individually for low-latency updates to SPI queues

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Visibility into the TX and RX FIFOs for ease of debugging

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FIFO Bypass Mode for low-latency updates to SPI queues

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Programmable transfer attributes on a per-frame basis:

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Parameterized number of transfer attribute registers (from two to eight)

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Serial clock with programmable polarity and phase

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Various programmable delays:

PCS to SCK delay

SCK to PCS delay

Delay between frames

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Programmable serial frame size of 4 to 16 bits, expandable with software control

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Continuously held chip select capability

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6 Peripheral Chip Selects, expandable to 64 with external demultiplexer

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Deglitching support for up to 32 Peripheral Chip Selects with external demultiplexer

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DMA support for adding entries to TX FIFO and removing entries from RX FIFO:

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TX FIFO is not full (TFFF)

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RX FIFO is not empty (RFDF)

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6 interrupt conditions:

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End of queue reached (EOQF)

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TX FIFO is not full (TFFF)

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Transfer of current frame complete (TCF)

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Attempt to transmit with an empty Transmit FIFO (TFUF)

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RX FIFO is not empty (RFDF)

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FIFO Underrun (slave only and SPI mode, the slave is asked to transfer data when

the TxFIFO is empty)

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FIFO Overrun (serial frame received while RX FIFO is full)

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Modified transfer formats for communication with slower peripheral devices

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Continuous Serial Communications Clock (SCK)

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Power savings via support for Stop Mode

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Enhanced DSI logic to implement a 32-bit Timed Serial Bus (TSB) configuration,

supporting the Microsecond Channel downstream frame format

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