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ST10F296 Datasheet(PDF) 340 Page - STMicroelectronics

Part # ST10F296
Description  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 Datasheet(HTML) 340 Page - STMicroelectronics

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Electrical characteristics
ST10F296E
340/346
Slave mode
VDD = 5 V ±10%, VSS = 0 V, TA = -40 to 125°C, CL = 50 pF
Table 180.
Slave mode
Symbol
Parameter
Max. baud rate 6.6 MBd
@FCPU = 40 MHz
(<SSCBR> = 0002h)(1)
Variable baud rate
(<SSCBR> = 0001h - FFFFh)
Unit
Min
Max
Min
Max
t310 (SR)
SSC clock cycle time(2)
150
150
8 TCL
262144 TCL
ns
t311 (SR)
SSC clock high time
63
-
t310/2 - 12
-
t312 (SR)
SSC clock low time
t313 (SR)
SSC clock rise time
-
10
-
10
t314 (SR)
SSC clock fall time
t315 (CC)
Write data valid after shift edge
55
2TCL + 30
t316 (CC)
Write data hold after shift edge
0
-
0
-
t317p (SR)
Read data setup time before latch
edge, phase error detection on
(SSCPEN = 1)
62
4TCL + 12
t318p (SR)
Read data hold time after latch
edge, phase error detection on
(SSCPEN = 1)
87
6TCL + 12
t317 (SR)
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
66
t318 (SR)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
31
2TCL + 6
1.
Maximum baud rate is 8 Mbaud and can be reached with 64 MHz CPU clock and <SSCBR> set to 3h, or with 48 MHz CPU
clock and <SSCBR> set to 2h. When 40 MHz CPU clock is used, the maximum baud rate cannot be higher than 6.6 Mbaud
(<SSCBR> = 2h) due to the limited granularity of <SSCBR>. A value of 1h for <SSCBR> may be used only with a CPU
clock lower than 32 MHz (after checking that timings are in line with the target slave).
2.
The formula for the SSC clock cycle time is:
t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC baud rate register, taken as an unsigned 16-bit integer. The minimum
limit allowed for t310 is 125 ns (corresponding to 8 Mbaud).
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