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ST10F296 Datasheet(PDF) 336 Page - STMicroelectronics

Part # ST10F296
Description  High performance 16-bit CPU with DSP functions
PDF  346 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F296 Datasheet(HTML) 336 Page - STMicroelectronics

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Electrical characteristics
ST10F296E
336/346
24.8.18
External bus arbitration
VDD = 5 V ±10 %, VSS = 0 V, TA = -40 to 125°C, CL = 50 pF.
Figure 117. External bus arbitration (releasing the bus)
1.
The ST10F296E completes the current running bus cycle before granting bus access.
2.
This is the first possibility for BREQ to become active.
3.
The CS outputs are resistive high (pull-up) after t64.
Table 178.
External bus arbitration
Symbol
Parameter
FCPU = 40 MHz
TCL = 12.5 ns
Variable CPU clock
1/2 TCL = 1 to 64 MHz
Unit
Min
Max
Min
Max
t61 (SR)
HOLD input setup time to
CLKOUT
18.5
-
18.5
-
ns
t62 (CC)
CLKOUT to HLDA high or
BREQ low delay
-
12.5
-
12.5
t63 (CC)
CLKOUT to HLDA low or
BREQ high delay
t64 (CC)
CSx release1
20
20
t65 (CC)
CSx drive
-4
15
-4
15
t66 (CC)
Other signals release1
-20
-
20
t67 (CC)
Other signals drive
-4
15
-4
15
t62
t61
t63
t66
(1)
t64
(1)
(2)
(3)
CLKOUT
HOLD
HLDA
BREQ
Others
CSx
(P6.x)
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Product(s)
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