ST72561AR7-Auto datasheet(224/324 Pages) STMICROELECTRONICS

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beCAN controller (beCAN)

ST72561-Auto

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Doc ID 12370 Rev 8

the software must release the output mailbox by setting the RFOM bit, so that a mailbox is

free to store the next valid message. Otherwise the next valid message received will cause a

loss of message.

Refer also to Message storage.

Overrun

Once the FIFO is in pending_3 state (that is, the three mailboxes are full) the next valid

message reception will lead to an overrun and a message will be lost. The hardware signals

the overrun condition by setting the FOVR bit in the CRFR register. Which message is lost

depends on the configuration of the FIFO:

●

If the FIFO lock function is disabled (RFLM bit in the CMCR register cleared) the last

message stored in the FIFO will be overwritten by the new incoming message. In this

case the latest messages will be always available to the application.

●

If the FIFO lock function is enabled (RFLM bit in the CMCR register set) the most

recent message will be discarded and the software will have the three oldest messages

in the FIFO available.

Reception related interrupts

On the storage of the first message in the FIFO - FMP[1:0] bits change from 00b to 01b - an

interrupt is generated if the FMPIE bit in the CIER register is set.

When the FIFO becomes full (that is, a third message is stored) the FULL bit in the CRFR

On overrun condition, the FOVR bit is set and an interrupt is generated if the FOVIE bit in

the CIER register is set.

17.4.3

Identifier filtering

In the CAN protocol the identifier of a message is not associated with the address of a node

but related to the content of the message. Consequently a transmitter broadcasts its

message to all receivers. On message reception a receiver node decides - depending on

the identifier value - whether the software needs the message or not. If the message is

needed, it is copied into the RAM. If not, the message must be discarded without

intervention by the software.

To fulfil this requirement, the beCAN controller provides six configurable and scalable filter

banks (0-5) in order to receive only the messages the software needs. This hardware

filtering saves CPU resources which would be otherwise needed to perform filtering by

software. Each filter bank consists of eight 8-bit registers, CFxR[0:7].

Scalable width

To optimize and adapt the filters to the application needs, each filter bank can be scaled

independently. Depending on the filter scale a filter bank provides:

●

One 32-bit filter for the STDID[10:0], IDE, EXTID[17:0] and RTR bits.

●

Two 16-bit filters for the STDID[10:0], RTR and IDE bits.

●

Four 8-bit filters for the STDID[10:3] bits. The other bits are considered as “don’t care”.

●

One 16-bit filter and two 8-bit filters for filtering the same set of bits as the 16 and 8-bit

filters described above.

Refer to Figure 102.

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