ST72561AR7-Auto datasheet(286/324 Pages) STMICROELECTRONICS

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Electrical characteristics

ST72561-Auto

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Doc ID 12370 Rev 8

20.9

I/O port pin characteristics

20.9.1

General characteristics

Subject to general operating conditions for VDD, fOSC, and TA unless otherwise specified.

Table 113.

I/O characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL

Input low level voltage(1)

CMOS ports

0.3 x VDD

VIH

Input high level voltage(1)

0.7 x VDD

Vhys

Schmitt trigger voltage hysteresis(2)

VIL

Input low level voltage(1)

TTL ports

0.8

VIH

Input high level voltage(1)

Vhys

Schmitt trigger voltage hysteresis(2)

400

IINJ(PIN)

Injected Current on PB3

VDD =5V

Flash devices

ROM devices

±4

Injected Current on any other I/O pin

±4

ΣIINJ(PIN)

(3)

Total injected current (sum of all I/O

and control pins)(4)

±25

Ilkg

Input leakage current on robust pins See Section 20.13: 10-bit ADC characteristics

Input leakage current(5)

VSS ≤VIN ≤VDD

±1

µA

Static current consumption(6)

Floating input mode

200

RPU

Weak pull-up equivalent resistor(7)

VIN = VS

VDD = 5V

250

CIO

I/O pin capacitance

tf(IO)out

Output high to low level fall time

CL = 50pF

Between 10% and 90%

tr(IO)out

Output low to high level rise time

tw(IT)in

External interrupt pulse time(4)

1tCPU

Data based on characterization results, not tested in production.

Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN)

specification. A positive injection is induced by VIN >VDD while a negative injection is induced by VIN <VSS. Refer to

Section 20.2: Absolute maximum ratings for more details.

To generate an external interrupt, a minimum pulse width must be applied on an I/O port pin configured as an external

interrupt source.

Leakage could be higher than max. if negative current is injected on adjacent pins.

Configuration not recommended, all unused pins must be kept at a fixed voltage: Using the output mode of the I/O, for

example, or an external pull-up or pull-down resistor (see Figure 126). Data based on design simulation and/or technology

characteristics, not tested in production.

The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics described in

Figure 127).

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