ST72561AR7-Auto datasheet(306/324 Pages) STMICROELECTRONICS

306 / 324 page

Device configuration and ordering information

ST72561-Auto

306/324

Doc ID 12370 Rev 8

Device configuration and ordering information

22.1

Introduction

Each device is available for production in user programmable versions (Flash) as well as in

factory coded versions (ROM/FASTROM).

ST72561-Auto devices are ROM versions. ST72P561-Auto devices are Factory Advanced

Service Technique ROM (FASTROM) versions: They are factory-programmed HDFlash

devices.

ST72F561-Auto Flash devices are shipped to customers with a default content (FFh), while

ROM factory coded parts contain the code supplied by the customer. This implies that Flash

devices have to be configured by the customer using the Option Bytes while the ROM

devices are factory-configured.

22.2

Flash devices

22.2.1

Flash configuration

The option bytes allows the hardware configuration of the microcontroller to be selected.

They have no address in the memory map and can be accessed only in programming mode

(for example using a standard ST7 programming tool). The default content of the Flash is

fixed to FFh. To program directly the Flash devices using ICP, Flash devices are shipped to

customers with a reserved internal clock source enabled. In masked ROM devices, the

option bytes are fixed in hardware by the ROM code (see option list).

Option byte 0

OPT7 = WDGHALT Watchdog reset on HALT

This option bit determines if a RESET is generated when entering HALT mode while the

Watchdog is active.

0: no reset generation when entering halt mode

1: reset generation when entering halt mode

OPT6 = WDGSW Hardware or software watchdog

This option bit selects the watchdog type.

0: hardware (watchdog always enabled)

1: software (watchdog to be enabled by software)

OPT5 = reserved, must be kept at default value.

OPT4 = LVD Voltage detection

This option bit enables the voltage detection block (LVD).

0: LVD on

1: LVD off

OPT3 = PLL OFF PLL activation

This option bit activates the PLL which allows multiplication by two of the main input clock

frequency. The PLL is guaranteed only with an input frequency between 2 and 4 MHz.

0: PLL x2 enabled

1: PLL x2 disabled

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