ST72561AR7-Auto datasheet(322/324 Pages) STMICROELECTRONICS

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Revision history

ST72561-Auto

322/324

Doc ID 12370 Rev 8

Revision history

Table 129.

Document revision history

Date

Revision

Changes

03-May-2004

Added TQFP 10x10 package

Removed internal RC

Updated Figure 11: Clock, reset and supply block diagram

Added note on monotonous VDD ramp on Section 5.6.1: Low voltage detector (LVD)

Added caution ART Ext clock not available in HALT see Section 11: PWM auto-

reload timer (ART)

Added note “Once the OCIE bit is set both output compare features may trigger...”

and “Once the ICIE bit is set both input capture features may trigger...” in 8-bit timer

Section 13: 8-bit timer (TIM8).

Changed clock from fcpu/8000 to fosc2/8000 in Section 13: 8-bit timer (TIM8)

Changed description of CSR register to read only except bit 2 R/W Section 13: 8-bit

timer (TIM8)

Added note to SPI slave freq. and updated Master mode procedure in Section 14:

Serial peripheral interface (SPI)

Changed description of NF bit in Section 15.10: LIN mode register description

Removed “Configurable timer resolution” under "Time triggered communication

option" from Section 17: beCAN controller (beCAN)

Added Clearing interrupts limitation and SCI wrong break duration to Chapter 24:

Important notes

Removed beCAN Time triggered mode feature from Section 17: beCAN controller

(beCAN)

Renamed CMSR RX and TX bits to REC and TRAN in Section 17: beCAN controller

(beCAN)

Added beCAN FIFO corruption limitation FIFO corruption

Modified IINJ for Port B3 in Section 20.9.1: General characteristics

11-May-2004

Modified Clearing interrupts limitation in Chapter 24: Important notes

12-May-2005

LIN

SCITM changed to LINSCITM throughout document.

Changed name of WWDGR register to WDGWR in Table 4: Hardware register map

Changed Static power consumption to 200 uA typ in Section 20.9.1: General

characteristics

Modified Readout Protection description in Section 3.3.1: Read-out protection

Added Section 24.1: All devices

Modified Figure 135: RESET pin protection when LVD is enabled and Figure 136:

RESET pin protection when LVD is disabled and related notes

Added 48K ROM version in Table 2: Product overview, Figure 5: Memory map and

Figure 154: ST72561xxx-Auto ROM commercial product structure

24-Oct-2005

Added standard version 16K ROM/Flash devices

Modified data retention in Section 20.7: Memory characteristics

Added “6” and “3” standard version device type coding to Figure 152: ST72F561xxx-

Auto Flash commercial product structure and Figure 154: ST72561xxx-Auto ROM

commercial product structure

Modified power consumption Section 20.4: Supply current characteristics

Added CDM in Electrostatic discharge (ESD)

Added “External interrupt missed” Section 24.1.3: External interrupt missed

ST72561AR7-Auto Datasheet(PDF) 322 Page - STMicroelectronics

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