STM32F302XD datasheet(119/168 Pages) STMICROELECTRONICS

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STM32F302xD STM32F302xE

Electrical characteristics

146

Figure 41. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 69. Otherwise the reset is not taken into account by the device.

3. Place the external capacitor 0.1u F on NRST as close as possible to the chip.

6.3.17

Timer characteristics

The parameters given in Table 70 are guaranteed by design.

Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 70. TIMx(1)(2) characteristics

1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM15, TIM16 and TIM17 timers.

2. Guaranteed by design, not tested in production.

Symbol

Parameter

Conditions

Min

Max

Unit

tres(TIM)

Timer resolution time

-1

tTIMxCLK

fTIMxCLK = 72 MHz

13.9

fTIMxCLK = 144 MHz

6.95

fEXT

Timer external clock

frequency on CH1 to CH4

-0

fTIMxCLK/2

MHz

fTIMxCLK = 72 MHz

MHz

ResTIM

Timer resolution

TIMx (except TIM2)

bit

TIM2

tCOUNTER 16-bit counter clock period

65536

tTIMxCLK

fTIMxCLK = 72 MHz

0.0139

910

µs

fTIMxCLK = 144 MHz

0.0069

455

µs

tMAX_COUNT

Maximum possible count

with 32-bit counter

65536 × 65536 tTIMxCLK

fTIMxCLK = 72 MHz

59.65

fTIMxCLK = 144 MHz

29.825

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