STM32F302XD datasheet(26/168 Pages) STMICROELECTRONICS

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Functional overview

STM32F302xD STM32F302xE

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DocID026900 Rev 4

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TIM2, 3, and TIM4

These are full-featured general-purpose timers:

–

TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler

–

TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.

These timers all feature 4 independent channels for input capture/output compare,

PWM or one-pulse mode output. They can work together, or with the other general-

purpose timers via the Timer Link feature for synchronization or event chaining.

The counters can be frozen in debug mode.

All have independent DMA request generation and support quadrature encoders.

•

TIM15, 16 and 17

These three timers general-purpose timers with mid-range features:

They have 16-bit auto-reload upcounters and 16-bit prescalers.

–

TIM15 has 2 channels and 1 complementary channel

–

TIM16 and TIM17 have 1 channel and 1 complementary channel

All channels can be used for input capture/output compare, PWM or one-pulse mode

output.

The timers can work together via the Timer Link feature for synchronization or event

chaining. The timers have independent DMA request generation.

The counters can be frozen in debug mode.

3.18.3

Basic timers (TIM6)

This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit

time base.

3.18.4

Independent watchdog (IWDG)

The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is

clocked from an independent 40 kHz internal RC and as it operates independently from the

main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog

to reset the device when a problem occurs, or as a free running timer for application timeout

management. It is hardware or software configurable through the option bytes. The counter

can be frozen in debug mode.

3.18.5

Window watchdog (WWDG)

The window watchdog is based on a 7-bit downcounter that can be set as free running. It is

used as a watchdog to reset the device when a problem occurs. It is clocked from the main

clock. It has an early warning interrupt capability and the counter can be frozen in debug

mode.

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