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USBN9602 Datasheet(PDF) 21 Page - National Semiconductor (TI) |
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USBN9602 Datasheet(HTML) 21 Page - National Semiconductor (TI) |
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21 / 45 page ![]() 10.0 Endpoint Operation (Continued) 21 www.national.com 10.4.1 RFxS Receive FIFO x Size. This is the total number of bytes available within the FIFO. 10.4.2 RXRP Receive Read Pointer. This pointer is incremented every time the firmware reads from the Receive FIFO. This pointer wraps around to zero if RFxS is reached. RXRP is never incremented beyond the value of RXWP. If the attempt is made to read more bytes than are actual- ly available (FIFO underrun), the last byte is read repeti- tively. You should therefore check RCOUNT to obtain an indication of the number of received bytes remaining. 10.4.3 RXWP Receive Write Pointer. This pointer is incremented every time the Endpoint controller writes to the Receive FIFO. This pointer wraps around to zero if RFxS is reached. A overrun condition occurs if RXRP equals RXWP and an attempt is made to receive more bytes. 10.4.4 RxFL Receive FIFO Level. This value indicates how many more bytes can be received until an overrun condition occurs with the next write to the FIFO. A FIFO warning can be issued if RxFL decreases to a specific value. The respective FWEV.RXWARNx bit is set if RxFL is equal to or less than the number specified with RXCx.RFWL. 10.4.5 RCOUNT Receive FIFO Count. This value indicates how many bytes are available to be read out of the Receive FIFO. This value is accessible by the firmware via the RFSx Register. 10.5 Programming Model Figure 19 illustrates the register hierarchy. It shows the re- lationship between the endpoint registers and event regis- ters. Figure 18. Rx FIFO Operation 0x0 + RXRP RXWP RFL = RXRP - RXWP (= RFxS - RCOUNT) Rx FIFO X + + RFxS - 1 FLUSH (resets RXRP and RXWP) RCOUNT = RXWP - RXRP |
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