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13

EN29F040

Rev. D, Issue Date: 2001/07/05

toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully

completed the program or erase operation. If it is still toggling, the device did not complete the operation

successfully, and the system must write the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read

cycles, determining the status as described in the previous paragraph. Alternatively, it may choose to

perform other system tasks. In this case, the system must start at the beginning of the algorithm when it

returns to determine the status of the operation (top of Flowchart 6).

Table 6. Status Register Bits

DQ

Name

Logic Level

Definition

‘1’

Erase Complete or

erase Sector in Erase suspend

‘0’

Erase On-Going

DQ7

Program Complete or

data of non-erase Sector during Erase

Suspend

7

DATA

POLLING

DQ7

Program On-Going

‘-1-0-1-0-1-0-1-’

Erase or Program On-going

DQ6

Read during Erase Suspend

6

TOGGLE

BIT

‘-1-1-1-1-1-1-1-‘

Erase Complete

‘1’

Program or Erase Error

5

ERROR BIT

‘0’

Program or Erase On-going

‘-1-0-1-0-1-0-1-’

Chip Erase, Erase or Erase suspend on

currently addressed

Sector. (When DQ5=1, Erase Error due to

currently addressed Sector. Program during

Erase Suspend on-going at current address

2

TOGGLE

BIT

DQ2

Erase Suspend read on

non Erase Suspend Sector

Notes:

DQ7

DQ5 for Program or Erase Success.

DQ6 Toggle Bit: remains at constant level when P/E operations are complete or erase suspend is acknowledged.

Successive reads output complementary data on DQ6 while programming or Erase operation are on-going.

DQ5 Error Bit: set to “1” if failure in programming or erase

DQ2 Toggle Bit: indicates the Erase status and allows identification of the erased Sector.