AS4C64M16D2 datasheet(39/58 Pages) ALSC

39 / 58 page

AS4C64M16D2

Alliance Memory Inc. reserves the right to change products or specification without notice.

Rev. 1.1

April. /2012

CK#

DQs

CMD

DQS

Tn-1

Tn+1

Tn+2

Tn+3

Tn+4

Tn+5

Post CAS#

READ A

NOP

Post CAS#

WRITE A

NOP

Dout A0

RL=5

DQS#

tRTW (Read to Write turn around time)

WL = RL-1 = 4

Dout A1

Dout A2

Dout A3

Din A0

Din A1

Din A2

Din A3

NOTE : The minimum time from the burst read command to the burst write command is defined by a read-to-write-

turn-around-time, which is 4 clocks in case of BL = 4 operation, 6 clocks in case of BL = 8 operation.

Figure 21. Seamless burst read operation: RL=5, AL=2, CL=3, BL=4

CK#

DQs

CMD

DQS

Post CAS#

READ A

NOP

Post CAS#

READ B

NOP

Dout A0

AL=2

DQS#

Dout A1

Dout A2

Dout A3 Dout B0

Dout B1 Dout B2

CL=3

RL=5

NOTE : The seamless burst read operation is supported by enabling a read command at every other clock for BL =

4 operation, and every 4 clock for BL =8 operation. This operation is allowed regardless of same or different banks

as long as the banks are activated.

Figure 22. Read burst interrupt timing: (CL=3, AL=0, RL=3, BL=8)

AS4C64M16D2 Datasheet(PDF) 39 Page - Alliance Semiconductor Corporation

AS4C64M16D2 Datasheet(HTML) 39 Page - Alliance Semiconductor Corporation

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