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AS4C64M32MD1-5BIN Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation

Part # AS4C64M32MD1-5BIN
Description  Power Down Mode
PDF  43 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4C64M32MD1-5BIN Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation

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AS4C64M32MD1
Confidential
Page 2
V.1.0 Sept. 2014
64M x 32 bit MOBILE DDR Synchronous DRAM (SDRAM)
Confidential
Advanced (Rev. 1.0, Sep. /2014)
Feature
-
4 banks x 16M x 32 organization
- Two Die-stacked 4 banks x 16M x 16
-
Data Mask for Write Control (DM)
-
Four Banks controlled by BA0 & BA1
-
Programmable CAS Latency: 2, 3
-
Programmable Wrap Sequence: Sequential
or Interleave
-
Programmable Burst Length:
2, 4, 8, for Sequential Type
-
2, 4, 8, for Interleave Type
-
Automatic and Controlled Precharge Command
-
Power Down Mode
-
Auto Refresh and Self Refresh
-
Refresh Interval: 8192 cycles/64ms
-
Available in 90-ball BGA
-
Double Data Rate (DDR)
-
Bidirectional Data Strobe (DQS) for input
and output data, active on both edges
-
Differential clock inputs CLK and /CLK
-
Power Supply 1.7V - 1.95V
-
Drive Strength (DS) Option:Full, 1/2, 1/4, 1/8
-
Auto Temperature-Compensated Self Refresh
(Auto TCSR)
-
Partial-Array Self Refresh (PASR) Option: Full,
1/2, 1/4, 1/8, 1/16
-
Deep Power Down (DPD) mode
-
Operating Temperature Range
-
Commercial 25°C to 85°C
-
Industrial-40°C to 85°C
All parts are ROHS Compliant
Description
The AS4C64M32MD1 is a four bank mobile
DDR DRAM organized as 4 banks x 16M x 32. It
achieves high speed data transfer rates by
employing a chip architecture that pre-fetches
multiple bits and then synchronizes the output data
to a system clock.
All of the controls, address, circuits are
synchronized with the positive edge of an
externally supplied clock. I/O transactions are
possible on both edges of DQS.
Operating the four memory banks in an inter-
leaved fashion allows random access operation to
occur at a higher rate than is possible with
standard DRAMs. A sequential and gapless data
rate is possible depending on burst length, CAS
latency and speed grade of the device.
Additionally, the device supports low power
saving features like PASR, Auto-TCSR, DPD as
well as options for different drive strength. It’s
ideally suitable for mobile application.
Table 1. Speed Grade Information
Speed Grade – Data rate Clock Frequency
CAS Latency
tRCD (ns)
tRP (ns)
400Mbps (max)
200 MHz (max)
3
15
15
Table 2 – Ordering Information for ROHS Compliant Products
Product part No
Org
Temperature
Package
AS4C64M32MD1-5BCN
64M x 32
Commercial - 0°C to 70°C
90-ball BGA
AS4C64M32MD1-5BIN
64M x 32
Industrial-40°C to 85°C
90-ball BGA



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