AS4C128M16D2 datasheet(39/75 Pages) ALSC

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AS4C128M16D2

Confidential

Version

2.0 – Oct/2014

Burst Write with Auto-Precharge

If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is engaged. The DDR2

SDRAM automatically begins precharge operation after the completion of the write burst plus the write recovery

time delay (WR), programmed in the MRS register, as long as tRAS is satisfied. The bank undergoing Auto-Precharge

from the completion of the write burst may be reactivated if the following two conditions are satisfied.

(1) The last data-in to bank activate delay time (tDAL = WR + tRP) has been satisfied.

(2) The RAS cycle time (tRC) from the previous bank activation has been satisfied.

In DDR2 SDRAMs the write recovery time delay (WR ) has to be programmed into the MRS mode register. As long as

the analog tWR timing parameter is not violated, WR can be programmed between 2 and 6 clock cycles. Minimum

Write to Activate command spacing to the same bank = WL + BL/2 + tDAL.

E xamples:

Burs t Write with Auto-Precharge (tRC Limit) : WL = 2, tDAL = 6 (WR = 3, tRP = 3) , BL = 4

CK, CK

CMD

WRITE A

NOP

Bank A

Activate

DQS,

DQS

A10 ="high"

Completion of the Burst Write

Auto-Precharge Begins

WL = RL-1 = 2

tDAL

tRP

DIN A0 DIN A1 DIN A2 DIN A3

tRCmin.

>=tRASmin.

BW-AP223

AS4C128M16D2 Datasheet(PDF) 39 Page - Alliance Semiconductor Corporation