ICS84329AM-01LF datasheet(2/20 Pages) IDT

2 / 20 page

84329AM-01

www.idt.com

REV. D

APRIL 9, 2014

84329-01

700MHZ, LOW JITTER, CRYSTAL-TO-3.3V

DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER

to the M divider and N output divider. On the LOW-to-HIGH

transition of the nP_LOAD input, the data is latched and the

M divider remains loaded until the next LOW transition on

nP_LOAD or until a serial event occurs. The TEST output is

Mode 000 (shift register out) when operating in the parallel

input mode. The relationship between the VCO frequency,

the crystal frequency and the M divider is defined as fol-

lows:

The M value and the required values of M0 through M8 are

shown in Table 3B, Programmable VCO Frequency Func-

tion Table. Valid M values for which the PLL will achieve

lock are defined as 200

≤ M ≤ 511. The frequency out is

defined as follows:

Serial operatio n oc cu rs when nP_L OAD is HIGH an d

S_LOAD is LOW. The shift register is loaded by sampling

the S_DATA bits with the rising edge of S_CLOCK. The con-

tents of the shift register are loaded into the M divider when

S_LOAD transitions from LOW-to-HIGH. The M divide and

N output divide values are latched on the HIGH-to-LOW

transition of S_LOAD. If S_LOAD is held HIGH, data at the

S_DATA input is passed directly to the M divider on each

rising edge of S_CLOCK. The serial mode can be used to

program the M and N bits and test bits T2:T0. The internal

registers T2:T0 determine the state of the TEST output as

follows:

FUNCTIONAL DESCRIPTION

NOTE: The functional description that follows describes

operation using a 16MHz crystal. Valid PLL loop divider

values for different crystal or input frequencies are defined

in the Input Frequency Characteristics, Table 6, NOTE 1.

The 84329-01 features a fully integrated PLL and there-

fore requires no external components for setting the loop

bandwidth. A series-resonant, fundamental crystal is used

as the input to the on-chip oscillator. The output of the oscil-

lator is divided by 16 prior to the phase detector. With a

16MHz crystal this provides a 1MHz reference frequency.

The VCO of the PLL operates over a range of 200MHz to

700MHz. The output of the M divider is also applied to the

phase detector.

The phase detector and the M divider force the VCO output

frequency to be M times the reference frequency ÷ 16 by

adjusting the VCO control voltage. Note that for some values

of M (either too high or too low), the PLL will not achieve lock.

The output of the VCO is scaled by a divider prior to being

sent to each of the LVPECL output buffers. The divider pro-

vides a 50% output duty cycle.

The programmable features of the ICS84329-01 support

two input modes to program the M divider and N output

divider. The two input operational modes are parallel and

serial. Figure 1 shows the timing diagram for each mode. In

parallel mode the nP_LOAD input is LOW. The data on in-

puts M0 through M8 and N0 through N1 is passed directly

fVCO =

fxtal x

fout =

fVCO

fxtal x

FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8, N0:N1

nP_LOAD

S_LOAD

TEST Output

Shift Register Out

High

PLL Reference Xtal ÷ 16

VCO ÷ M (non 50% Duty M divider)

fOUT

LVCMOS Output Frequency < 200MHz

Low

S_CLOCK ÷ M

(non 50% Duty Cycle M divider)

fOUT ÷ 4

fOUT

S_CLOCK ÷ N divider

fOUT

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