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A3948SLB Datasheet(PDF) 2 Page - Allegro MicroSystems

Part # A3948SLB
Description  DMOS Full-Bridge PWM Motor Driver
PDF  13 Pages
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Manufacturer  ALLEGRO [Allegro MicroSystems]
Direct Link  http://www.allegromicro.com
Logo ALLEGRO - Allegro MicroSystems

A3948SLB Datasheet(HTML) 2 Page - Allegro MicroSystems

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3948
DMOS FULL-BRIDGE PWM
MOTOR DRIVER
Always order by complete part number:
Part Number
Package
RθθθθθJA
RθθθθθJT
A3948SB
24-pin batwing DIP
40
°C/W
6
°C/W
A3948SLB
24-lead batwing SOIC
77
°C/W
6
°C/W
Designed for pulse-width modulated (PWM) current control of dc
motors, the A3948SB and A3948SLB are capable of continuous output
currents to
±1.5 A and operating voltages to 50 V. Internal fixed off-
time PWM current-control timing circuitry can be programmed via a
serial interface to operate in slow, fast, and mixed current-decay
modes. Similar devices with outputs rated to
±2 A are available as the
A3958SB/SLB.
PHASE and ENABLE input terminals are provided for use in
controlling the speed and direction of a dc motor with externally
applied PWM-control signals. The ENABLE input can be
programmed via the serial port to PWM the bridge in fast or slow
current decay. Internal synchronous rectification control circuitry is
provided to reduce power dissipation during PWM operation.
Internal circuit protection includes thermal shutdown with
hysteresis, and crossover-current protection. Special power-up
sequencing is not required.
The A3948SB/SLB is supplied in a choice of two power
packages, a 24-pin plastic DIP with a copper batwing tab (package
suffix ‘B’), and a 24-lead plastic SOIC with a copper batwing tab
(package suffix ‘LB’). In both cases, the power tab is at ground
potential and needs no electrical isolation.
FEATURES
s
±1.5 A, 50 V Continuous Output Rating
s Low r
DS(on) Outputs
s Programmable Mixed, Fast, and Slow Current-Decay Modes
s Serial Interface Controls Chip Functions
s Synchronous Rectification for Low Power Dissipation
s Internal UVLO and Thermal-Shutdown Circuitry
s Crossover-Current Protection
A3948SLB (SOIC)
VBB
24
23
22
21
20
19
18
17
16
15
14
13
GROUND
GROUND
RANGE
NO
CONNECTION
OUTB
LOAD SUPPLY
SENSE
OUTA
NO
CONNECTION
MODE
REF
VREG
Dwg. PP-069A
1
2
3
4
5
6
7
8
9
12
11
10
9
GROUND
GROUND
CP
CP2
CP1
PHASE
VDD
ENABLE
DATA
CLOCK
STROBE
LOGIC SUPPLY
θ
OSC
NC
NC
÷
ABSOLUTE MAXIMUM RATINGS
Load Supply Voltage, VBB .................. 50 V
Output Current, IOUT........................ ±1.5 A
Logic Supply Voltage, VDD ................ 7.0 V
Input Voltage, VIN .... -0.3 V to VDD + 0.3 V
Sense Voltage, VS .......................... 0.55 V
Reference Voltage, VREF .................. 5.5 V
Package Power Dissipation (TA = 25°C), PD
A3948SB ................................. 3.1 W*
A3948SLB ............................... 1.6 W*
Operating Temperature Range,
TA ............................... -20°C to +85°C
Junction Temperature,
TJ ............................................ +150°C
Storage Temperature Range,
TS ............................. -55°C to +150°C
Output current rating may be limited by duty cycle,
ambient temperature, and heat sinking. Under any
set of conditions, do not exceed the specified
current rating or a junction temperature of 150
°C.
* Per SEMI G42-88 Specification.
Note that the A3948SLB(SOIC) and A3948SB
(DIP) do not share a common terminal
assignment.



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