AS3636 datasheet(7/42 Pages) AMSCO

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AS3636

Preliminary Datasheet, Confidential - E l e c t r i c a l C h a r a c t e r i s t i c s

Timing Diagrams

Figure 3. I

2C mode Timing Diagram

Turns Ratio

for VFLASH=330V (final charged

voltage on CFLASH)

10.2

VISOLATION

Isolation Voltage

500

ISATURATION

Primary Saturation

Current

0.84

RPRIMARY

Primary Winding

Resistance

0.4

RSECUNDAR

Secondary Winding

Resistance

1. The overvoltage protection of the DCDC step up converter (pin VOUTBOOST) will trigger above 5.4V thus

shutting down the DCDC converter.

2. ISHUTDOWN or ISTANBY includes leakage current for SW_B and SW_F.

3. Due to slope compensation of the current limit, ILIMIT changes with duty cycle.

4. After this period, the first clock pulse is generated.

5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the

SCL signal) to bridge the undefined region of the falling edge of SCL.

6. A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT = to 250ns must then

be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such a

device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line tR max +

tSU:DAT = 1000 + 250 = 1250ns before the SCL line is released.

Table 3. Electrical Characteristics (Continued)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

SCL

SDA

tBUF

tHD:STA

tSU:STA

REPEATED

START

tSU:STO

tSU:DAT

tHIGH

tHD:DAT

tLOW

tHD:STA

START

STOP

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