RH56D-PCI datasheet(13/60 Pages) ETC

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RH56D-PCI Modem Designer’s Guide

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Conexant

1-7

Conexant Proprietary Information

Voice/TAM Mode

Voice/TAM Mode features include 8-bit

µ-Law, A-Law, and linear coding at 8000 Hz and 7200 Hz sample rates. Tone

detection/generation, call discrimination, and concurrent DTMF detection are also supported. ADPCM (4-bit IMA) coding is

also supported to meet Microsoft WHQL logo requirements.

Voice/TAM Mode is supported by three submodes:

Online Voice Command Mode supports connection to the telephone line or, for the SP model, a handset.

Voice Receive Mode supports recording voice or audio data input at the RIN pin, typically from the telephone line or, for

the SP model, a microphone/handset.

Voice Transmit Mode supports playback of voice or audio data to the TXA1/TXA2 output, typically to the telephone line

or, for the SP model, a speaker/handset.

Speakerphone Mode (SP Model)

The SP model includes additional telephone handset, external microphone, and external speaker interfaces which support

voice and full-duplex speakerphone (FDSP) operation.

Hands-free full-duplex telephone operation is supported in Speakerphone Mode under host control. Speakerphone Mode

features an advanced proprietary speakerphone algorithm which supports full-duplex voice conversation with acoustic, line,

and handset echo cancellation. Parameters are constantly adjusted to maintain stability with automatic fallback from full-

duplex to pseudo-duplex operation. The speakerphone algorithm allows position independent placement of microphone and

speaker. The host can separately control volume, muting, and AGC in microphone and speaker channels.

1.3.4 Hardware Interfaces

PCI Bus Host Interface

The Bus Interface conforms to the PCI Local Bus Specification, Production Version, Revision 2.1, June 1, 1995. It is a

memory slave (burst transactions) and a bus master for PC host memory accesses (burst transactions). Configuration is by

PCI configuration protocol.

The following interface signals are supported:

• Address and data

− 32 bidirectional Address/Data (AD[31-0]; bidirectional

− Four Bus Command and Byte Enable (CBE [3:0]), bidirectional

− Bidirectional Parity (PAR); bidirectional

• Interface control

− Cycle Frame (FRAME#); bidirectional

− Initiator Ready (IRDY#); bidirectional

− Target Ready (TRDY#); bidirectional

− Stop (STOP#); bidirectional

− Initialization Device Select (IDSEL); input

− Device Select (DEVSEL#); bidirectional

• Arbitration

− Request (REQ#); output

− Grant (GRANT#); input

• Error reporting

− Parity Error (PERR#); bidirectional

− System Error ; bidirectional

• System

− Interrupt A (INTA#); output

− Clock (PCICLK); input

− Reset (PCIRST#); input

• Power Management

− Power Management Event (PME#), output

− Vaux Detect (VauxDET), input

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