USBUF01P6

5/7

®

Fig. A5: USBUF01P6 ESD clamping behavior.

Fig. A6: Measurement board.

To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical

Vinput = 55.48 V

Voutput = 10.36 V

This confirms the very low remaining voltage across the device to be protected. It is also important to note

that in this approximation the parasitic inductance effect was not taken into account. This could be few

tenths of volts during few ns at the Vinput side. This parasitic effect is not present at the Voutput side due

The measurements done hereafter show very clearly (fig. A7) the high efficiency of the ESD protection :

- no influence of the parasitic inductances on Voutput stage

voltage) in the negative way

ESD Surge

Vinput

Voutput

Rload

Rg

Rt

S1

Rd

V

BR

V

BR

V

PP

Device

to be

protected

USBUF01P6

Rd

S2

TEST BOARD

ESD

SURGE

15kV

Air

Discharge

Vin

Vout

Vinput

R

g

V

BR

R

d

V

g

⋅

+

⋅

R

g

-----------------------------------------------

=

Voutput

R

t

V

BR

R

d

Vinput

⋅

+

⋅

R

t

----------------------------------------------------------

=