AT91SAM7X512 datasheet(13/44 Pages) ATMEL

13 / 44 page

6120DS–ATARM–03-Oct-06

AT91SAM7X512/256/128 Preliminary Summary

I/O Lines Considerations

6.1

JTAG Port Pins

TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not

integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The

JTAGSEL pin integrates a permanent pull-down resistor of about 15 k

Ω to GND, so that it can be

left unconnected for normal operations.

6.2

Test Pin

Th e T S T p i n is used f o r ma nu f a ct ur in g t e st o r f a st pr og ra mmi ng mod e of t h e

AT91SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down

resistor of about 15 k

Ω to GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high

and PA2 tied to low.

Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

6.3

Reset Pin

The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset

controller and can be driven low to provide a reset signal to the external components or asserted

low externally to reset the microcontroller. There is no constraint on the length of the reset pulse,

and the reset controller can guarantee a minimum pulse length. This allows connection of a sim-

ple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset

all the components of the system.

The NRST pin integrates a permanent pull-up resistor to VDDIO

6.4

ERASE Pin

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a

permanent pull-down resistor of about 15 k

Ω to GND, so that it can be left unconnected for nor-

mal operations.

This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to

high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high

during more than 220 ms to perform the re-initialization of the Flash.

6.5

PIO Controller Lines

All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programma-

ble pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O

line through the PIO controllers.

5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be

driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while

the programmable pull-up resistor is enabled will create a current path through the pull-up resis-

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