MAS3587F datasheet(16/82 Pages) MICRONAS

16 / 82 page

MAS 3587F

ADVANCE INFORMATION

Micronas

2.13.3. Control of the Signal Processing

Before starting the DSP, the controller should check for

a sufficient voltage supply (respective flag PUPn at I2C

subaddress 76hex). The DSP is enabled by setting the

appropriate bit in the Control register (I2C subaddress

6ahex). The nominal frequency of the crystal oscillator

must be written into D0:7f3. After an initialization

phase of 5 ms, the DSP data registers can be

accessed via I2C (see Table 3–3 on page 20).

Input and output control is performed via memory loca-

tion D0:7f1 and D0:7f2. The parallel interface (PIO) is

the default setting for compressed data. The decoded

audio can be routed to either the SPDIF, the SDO and

the analog outputs. The output clock signal at pin

CLKO is defined in D0:7f4. The specific settings for

audio encoding are written to memory location D0:7f0

(continued).

All changes in the D0-memory cells become effective

synchronously upon setting the LSB of Main I/O Con-

trol (see Table 3–7 on page 34).

The common way to start encoding or decoding is to

perform all necessary settings and switch on the appli-

cation by selecting the desired bit(s) in the Application

Selection memory cell (D0:7f6) (see Table 3–6 on

page 33).

The digital volume control (see Table 3–7 on page 34)

is applied to the output signal of the DSP. The decoded

audio data is by default available at the SPDIF 1 output

interface (for MPEG 1 sampling frequencies).

The DSP does not have to be started if its functions

are not needed, e.g. for routing audio via the A/D and

the D/A converters through the codec part of the IC.

2.13.4. Start-up of the Audio Codec

(see Table 3–3 on page 20)

Before enabling the audio codec, the controller should

check for a sufficient voltage supply (respective flag

PUPn at I2C subaddress 76hex).

The audio codec is enabled by setting the appropriate

bit at the Control register (I2C subaddress 6ahex). After

an initialization phase of 5 ms, the DSP data registers

can be accessed via I2C. The A/D and the D/A con-

verters must be switched on explicitly (00 00hex at I

subaddress 6chex). The D/A converters may either

accept data from the A/D converters or the output of

the DSP, or a mix of both (register 00 06hex and 00

07hex at I

2C subaddress 6c

hex). Finally, an appropriate

output volume (00 10hex at I

2C subaddress 6c

hex) must

be selected.

2.13.5. Power-Down (see Table 3–3 on page 20)

All analog outputs should be muted and the A/D and

the D/A converters must be switched off (register

00 10hex and 00 00hex at I

2C subaddress 6c

hex). The

DSP and the audio codec must be disabled (clear

DSP_EN and CODEC_EN bits in the Control register,

I2C subaddress 6ahex). By clearing both DC/DC

enable flags in the Control register (I2C subaddress

6ahex), the microcontroller can power down the com-

plete system.

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