EPC901 datasheet(34/37 Pages) EPC

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15. Self-test mode by fill-and-spill

Instead of generating charge in the CCD by photo-electrical conversion, charge can also be generated electrically by the as-called fill-and-

spill circuitry. To use the fill-and-spill circuitry, the IC has to be forced into test mode.

The basic behavior of the IC by the fill-and-spill circuitry is exactly the same as when the IC is illuminated. I.e. also when fill-and-spill is

used, the acquisition is controlled by SHUTTER, the internal flush and shift operation are similar and the signal DATA_RDY is asserted at

the end of the internal shift operation.

If the CCD is stimulated by the fill-and-spill circuitry, the on-chip test controller coordinates the operation of the fill-and-spill circuitry and the

CCD. The following features of fill-and-spill can be controlled:

■ number of electrons that are injected into the CCD per fill-and-spill cycle (pins ANA_TEST_*)

■ number of fill-and-spill cycles per acquisition (register ANA_TEST_CONF)

■ selection of which pixels are stimulated by fill-and-spill (register ANA_TEST_CONF)

The number of electrons that are injected into each pixel of the CCD during each fill-and-spill cycle depends on the voltages VIN and VDC.

The two voltage levels VIN and VDC are provided through the analog test pads ANA_TEST*.

QFILL_SPILL

VIN - VDC

QFILL_SPILL

VIN - VDC

< 0

220k

1.56

20k

0.44

240k

1.65

40k

0.60

260k

1.75

60k

0.72

280k

1.85

80k

0.84

300k

1.95

100k

0.95

320k

2.06

120k

1.06

340k

2.17

140k

1.16

360k

2.27

160k

1.27

380k

2.36

180k

1.37

400k

2.54

200k

1.46

The number of fill-and-spill cycles per acquisition can be configured by NUM_FILL_SPILL_CYC in register ANA_TEST_CONF (see Table

32). The duration of one fill-and-spill cycle is TCYC,FILL_SPILL (see Table 31). In order to allow the full fill-and-spill operation to terminate the

complete fill-and-spill operation, SHUTTER has to remain asserted for at least NUM_FILL_SPILL_CYC * TCYC,FILL_SPILL after the end of the

internal flush operation (see Figure 19).

Flush

Shift

SHUTTER

CCD operation

Fill-and-spill

FLUSH

SHIFT

> NUM_FILL_SPILL_CYC * T

CYC,FILL_SPILL

DATA_RDY

Figure 19: Timing diagram of a fill-and-spill operation of the CCD

Parameter

Description

Min

Typ

Max

Unit

VIN

Voltage range of fill_spill_vin_packet_AI

1.5

VDC

Voltage range of fill_spill_vdc_AI

TCYC,FILL_SPILL

Duration of one fill-and-spill cycle

175

Table 31: Parameters for the fill-and-spill operation

Register bits 3 to 6 of ANA_TEST_CONF are used in fill-and-spill test mode to configure into which pixels charge shall be spilled (see Ta-

ble 32).

Characteristics subject to change without notice

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