LTC3733 datasheet(21/32 Pages) LINER

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LTC3733/LTC3733-1

3733f

The emitter of Q1 will hold up the EAIN pin to a voltage in

the absence of VOUT that will prevent the internal sensing

circuitry from reducing the peak output current. Remov-

ing the function in this manner eliminates the external

MOSFET’s protective feature under short-circuit condi-

tions. This technique will also prevent the short-circuit

latchoff function from turning off the part during a short-

circuit event and the output current will only be limited to

N • 75mV/RSENSE.

Undervoltage Reset

In the event that the input power source to the IC (VCC)

drops below 4V, the SS capacitor will be discharged to

ground and the controller will be shut down. When VCC

rises above 4V, the SS capacitor will be allowed to re-

charge and initiate another soft-start turn-on attempt. This

may be useful in applications that switch between two

supplies that are not diode connected, but note that this

cannot make up for the resultant interruption of the

regulated output.

Phase-Locked Loop and

Frequency Synchronization (LTC3733-1)

The IC has a phase-locked loop comprised of an internal

voltage controlled oscillator and phase detector. This

allows the top MOSFET of output stage 1’s turn-on to be

locked to the rising edge of an external source. The

frequency range of the voltage controlled oscillator is

±50% around the center frequency fO. A voltage applied to

the PLLFLTR pin of 1.2V corresponds to a frequency of

approximately 350kHz. The nominal operating frequency

range of the IC is 210kHz to 530kHz.

The phase detector used is an edge sensitive digital type

that provides zero degrees phase shift between the

external and internal oscillators. This type of phase

detector will not lock the internal oscillator to harmonics

of the input frequency. The PLL hold-in range,

∆fH, is

equal to the capture range,

∆fC:

∆fH = ∆fC = ±0.5 fO

The output of the phase detector is a complementary pair

of current sources charging or discharging the external

filter components on the PLLFLTR pin. A simplified block

diagram is shown in Figure 9.

If the external frequency (fPLLIN) is greater than the oscil-

lator frequency, fOSC, current is sourced continuously,

pulling up the PLLFLTR pin. When the external frequency

is less than fOSC, current is sunk continuously, pulling

down the PLLFLTR pin. If the external and internal fre-

quencies are the same, but exhibit a phase difference, the

current sources turn on for an amount of time correspond-

ing to the phase difference. Thus, the voltage on the

PLLFLTR pin is adjusted until the phase and frequency of

the external and internal oscillators are identical. At this

stable operating point, the phase comparator output is

open and the filter capacitor CLP holds the voltage. The IC

PLLIN pin must be driven from a low impedance source

such as a logic gate located close to the pin. When using

multiple ICs for a phase-locked system, the PLLFLTR pin

of the master oscillator should be biased at a voltage that

will guarantee the slave oscillator(s) ability to lock onto the

master’s frequency. A voltage of 1.7V or below applied to

the master oscillator’s PLLFLTR pin is recommended in

order to meet this requirement. The resultant operating

frequency will be approximately 500kHz for 1.7V.

APPLICATIO S I FOR ATIO

EXTERNAL

OSC

2.4V

RLP

10k

CLP

OSC

DIGITAL

PHASE/

FREQUENCY

DETECTOR

PHASE

DETECTOR/

OSCILLATOR

PLLIN

(LTC3733-1

ONLY)

3733 F09

PLLFLTR

50k

Figure 9. Phase-Locked Loop Block Diagram

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