R5F10268ASP datasheet(32/110 Pages) RENESAS

32 / 110 page

RL78/G12

2. ELECTRICAL SPECIFICATIONS (TA =

40 to +85C)

R01DS0193EJ0210 Rev.2.10

Mar 25, 2016

Page 32 of 106

(2) During communication at same potential (CSI mode) (master mode, SCK00... internal clock output,

corresponding CSI00 only)

(TA =

40 to +85C, 2.7 V  VDD  5.5 V, VSS = 0 V)

HS (high-speed main)

Mode

LS (low-speed main)

Mode

Parameter

Symbol

Conditions

MIN.

MAX.

MIN.

MAX.

Unit

SCK00 cycle time

tKCY1

 2/fCLK

83.3

250

4.0 V

 VDD  5.5 V

tKCY1/2

7

tKCY1/2

50

SCK00 high-/low-

level width

tKH1,

tKL1

2.7 V

 VDD  5.5 V

tKCY1/2

10

tKCY1/2

50

4.0 V

 VDD  5.5 V

110

SI00 setup time

(to SCK00

) Note 1

tSIK1

2.7 V

 VDD  5.5 V

110

SI00 hold time

(from SCK00

) Note2

tKSI1

Delay time from

SCK00

 to SO00

output

Note 3

tKSO1

C = 20 pF

Note 4

Notes 1.

When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to

SCK00

” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from

SCK00

” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes

“from SCK00

” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.

C is the load capacitance of the SCK00 and SO00 output lines.

Caution

Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00 pins by

using port input mode register 1 (PIM1) and port output mode register 1 (POM1).

Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.

2. fMCK: Serial array unit operation clock frequency

(Operation clock to be set by the serial clock select register 0 (SPS0) and the CKS00 bit of serial mode

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