WM9710

Production Data

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PD Rev 4.0 December 2003

15

3-D STEREO ENHANCEMENT

This device contains a stereo enhancement circuit, designed to optimise the listening experience

when the device is used in a typical PC operating environment. That is, with a pair of speakers

placed either side of the monitor with little spatial separation. This circuit creates a difference

signal by differencing left and right channel playback data, then filters this difference signal using

lowpass and highpass filters whose time constants are set using external capacitors connected to

the CX3D pins 33 and 34. Typically the values of 100nF and 47nF set highpass and lowpass

poles at about 100Hz and 1kHz respectively. This frequency band corresponds to the range over

which the ear is most sensitive to directional effects.

The filtered difference signal is gain adjusted by an amount set using the 4-bit value written to

Register 22h bits 3 to 0. Value 0h is disable, value Fh is maximum effect. Typically a value of 8h

is optimum. The user interface would most typically use a slider type of control to allow the user to

adjust the level of enhancement to suit the program material. Bit D13 3D in Register 20h is the

overall 3D enable bit. The Reset Register 00h reads back the value 11000 in bits D14 to D10.

This corresponds to decimal 24, which is registered with Intel as Wolfson Stereo Enhancement.

Note that the external capacitors setting the filtering poles applied to the difference signal may be

adjusted in value, or even replaced with a direct connection between the pins. If such adjustments

are made, then the amount of difference signal fed back into the main signal paths may be

significant, and can cause large signals which may limit, distort, or overdrive signal paths or

speakers. Adjust these values with care, to select the preferred acoustic effect. There is no

provision for pseudo-stereo effects. Mono signals will have no enhancement applied (if the signals

are in phase and of the same amplitude). Signals from the PCM DAC channels can have stereo

enhancement applied. It can also be bypassed if desired. This function is enabled by setting the

bit POP in Register 20h.

VARIABLE SAMPLE RATE SUPPORT

The DACs and ADCs on this device support all the recommended sample rates specified in the

Intel AC’97 rev2.1 & rev2.2 specifications for audio rates. The default rate is 48kHz. If alternative

rates are selected and variable rate audio is enabled (Register 2Ah, bit 0), the AC’97 interface

continues to run at 48k words per second, but data is transferred across the link in bursts such

that the net sample rate selected is achieved. It is up to the AC’97 Revision 2.1/2 compliant

controller to ensure that data is supplied to the AC link, and received from the AC link, at the

appropriate rate.

Variable rates are selected by writing to registers 2Ch (DAC) and 32h (ADC). ADC and DAC rates

may be set independently, with left and right channels always at the same rate. The device

supports on demand sampling. That is, when the DAC signal processing circuits need another

sample, a sample request is sent to the controller which must respond with a data sample in the

next frame it sends. For example, if a rate of 24kHz is selected, on average the device will

request a sample from the controller every other frame, for each of the stereo DACs. Note that if

an unsupported rate is written to one of the rate registers, the rate will default to the nearest rate

supported. The Register will then respond, when interrogated, with the supported rate the device

has defaulted to.

The WM9710 clocks will scale automatically dependent upon the MCLK frequency, where MCLK

is not equal to 24.576MHz. With a 24MHz clock the BCLK frequency expected will be 12MHz and

the sampling frequency (SYNC0 expected is BCLK/256 = 46.875kHz.

AUDIO

SAMPLE RATE

CONTROL VALUE

D15-D0

8000

1F40

11025

2B11

16000

3E80

22050

5622

32000

7D000

44100

AC44

48000

BB80

Table 1 Variable Sample Rates Supported