HT86A72 datasheet(28/68 Pages) HOLTEK

28 / 68 page

HT86Axx/HT86ARxx

Rev. 1.10

December 12, 2012

Note that to achieve a maximum full range count of FFH

for the 8-bit timer, the preload registers must first be

cleared to all zeros. It should be noted that after

power-on, the preload registers will be in an unknown

condition. Note that if the Timer Counters are in an OFF

condition and data is written to their preload registers,

this data will be immediately written into the actual coun-

ter. However, if the counter is enabled and counting, any

new data written into the preload data register during

this period will remain in the preload register and will

only be written into the actual counter the next time an

overflow occurs. Note also that when the timer registers

are read, the timer clock will be blocked to avoid errors,

however, as this may result in certain timing errors, pro-

grammers must take this into account.

Timer Control Registers

TMR0C, TMR1C, TMR2C, TMR3C

The timers are setup using their respective control regis-

ter. These registers are known as TMR0C, TMR1C,

TMR2C and TMR3C. It is the timer control register to-

gether with its corresponding timer registers that control

the full operation of the Timer. Before the timers can be

used, it is essential that the appropriate timer control

its correct operation, a process that is normally carried

out during program initialization.

Bits 7 and 6 of the Timer Control Register, which are

known as the bit pair TM1/TM0, must be set to 10 re-

spectively to ensure correct Timer operation. The

timer-on bit, which is bit 4 of the Timer Control Register

and known as TON, provides the basic on/off control of

the respective timer. setting the bit high allows the timer

to run, clearing the bit stops the timer. Bits 0~2 of the

Timer Control Register determine the division ratio of

the input clock prescaler.

Configuring the Timer

The Timer is used to measure fixed time intervals, pro-

viding an internal interrupt signal each time the Timer

overflows. To do this the Operating Mode Select bit pair

in the Timer Control Register must be set to the correct

value as shown.

The Timer clock source is further divided by a prescaler,

the value of which is determined by the Prescaler Rate

Select bits, which are bits 0~2 in the Timer Control Reg-

ister. After the other bits in the Timer Control Register

have been setup, the enable bit, which is bit 4 of the

Timer Control Register, can be set high to enable the

Timer to run. Each time an internal clock cycle occurs,

the Timer increments by one. When it is full and over-

flows, an interrupt signal is generated and the Timer will

reload the value already loaded into the preload register

and continue counting. The interrupt can be disabled by

ensuring that the Timer Interrupt Enable bit in the Inter-

rupt Control Register, INTC, is reset to zero.

T i m e r M o d e C o n t r o l

T 3 O N

P r e l o a d R e g i s t e r

T i m e r

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

T 3 P S C 2 ~ T 3 P S C 0

8 - B i t T i m e r

f S Y S / 4

P r e s c a l e r

( 1 / 2 ~ 1 / 2 5 6 )

T 3 T M 1

T 3 T M 0

R T C

M U X

C o n f i g u r a t i o n

O p t i o n

8-bit Timer Structure

- TMR3

I n c r e m e n t

T i m e r C o n t r o l l e r

P r e s c a l e r O u t p u t

T i m e r + 1

T i m e r + 2

T i m e r + N

T i m e r + N + 1

Timer Mode Timing Diagram

HT86A72 Datasheet(PDF) 28 Page - Holtek Semiconductor Inc

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