HT86AR72 datasheet(48/68 Pages) HOLTEK

48 / 68 page

HT86Axx/HT86ARxx

Rev. 1.10

December 12, 2012

S B C R R e g i s t e r

b 7

b 0

C K S

M 1

M 0

S B E N M L S C S E N W C O L T R F

T r a n s m i t t / R e c e i v e F l a g

0 : N o t c o m p l e t e

1 : T r a n s m i s s i o n / r e c e p t i o n c o m p l e t e

W r i t e C o l l i s i o n B i t

0 : C o l l i s i o n f r e e

1 : C o l l i s i o n d e t e c t e d

S e l e c t i o n S i g n a l E n a b l e / D i s a b l e B i t

0 : S C S f l o a t i n g

1 : E n a b l e

M S B / L S B F i r s t B i t

0 : L S B s h i f t f i r s t

1 : M S B s h i f t f i r s t

S e r i a l B u s E n a b l e / D i s a b l e B i t

0 : D i s a b l e

1 : E n a b l e

D e p e n d e n t u p o n C S E N b i t

M a s t e r / S l a v e / B a u d R a t e B i t s

M a s t e r , b a u d r a t e : f S I O

M a s t e r , b a u d r a t e : f S I O / 4

M a s t e r , b a u d r a t e : f S I O / 1 6

S l a v e m o d e

M 1

M 0

C l o c k S o u r c e S e l e c t B i t

0 : f S I O = f S Y S / 4

1 : f S I O = f S Y S

SPI Interface Control Register

S C K

S C S

S D I

S D O

D 1 / D 6

D 7 / D 0 D 6 / D 1 D 5 / D 2 D 4 / D 3 D 3 / D 4 D 2 / D 5 D 1 / D 6 D 0 / D 7

D 7 / D 0 D 6 / D 1 D 5 / D 2 D 4 / D 3 D 3 / D 4 D 2 / D 5

D 0 / D 7

S B E N = C S E N = 1 a n d w r i t e d a t a t o S B D R

S B E N = 1 , C S E N = 0 a n d w r i t e d a t a t o S B D R ( i f p u l l - h i g h e d )

S C K

SPI Bus Timing

SPI Registers

There are two registers associated with the SPI Inter-

face. These are the SBCR register which is the control

SBCR register is used to setup the required setup pa-

rameters for the SPI bus and also used to store associ-

ated operating flags, while the SBDR register is used for

data storage.

After Power on, the contents of the SBDR register will be

in an unknown condition while the SBCR register will de-

fault to the condition below:

CKS M1 M0 SBEN MLS CSEN WCOL TRF

00000

Note that data written to the SBDR register will only be

written to the TXRX buffer, whereas data read from the

SBDR register will actual be read from the register.

SPI Bus Enable/Disable

To enable the SPI bus and CSEN=1, the SCK, SDI,

SDO and SCS lines should all be zero, then wait for data

to be written to the SBDR (TXRX bufffer) register. For

the Master Mode, after data has been written to the

SBDR (TXRX buffer) register then transmission or re-

ception will start automatically. When all the data has

been transferred the TRF bit should be set. For the

Slave Mode, when clock pulses are received on SCK,

data in the TXRX buffer will be shifted out or data on SDI

will be shifted in.

To Disable the SPI bus SCK, SDI, SDO, SCS floating.

SPI Operation

All communication is carried out using the 4-line inter-

face for both Master or Slave Mode. The timing diagram

shows the basic operation of the bus.

HT86AR72 Datasheet(PDF) 48 Page - Holtek Semiconductor Inc

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