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HT24LC04 Datasheet(PDF) 4 Page - Holtek Semiconductor Inc |
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HT24LC04 Datasheet(HTML) 4 Page - Holtek Semiconductor Inc |
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4 / 12 page  Rev. 1.80 4 January 16, 2014 HT24LC04 Functional Description • Serialclock–SCL TheSCLinputisusedforpositiveedgeclock dataintoeachEEPROMdeviceandnegativeedge clockdataoutofeachdevice. • Serialdata–SDA The SDA pin is bidirectional for serial data transfer.Thepinisopen-draindrivenandmaybe wired-ORwithanynumberofotheropen-drainor opencollectordevices. • AddressInputs–A0,A1,A2 TheHT24LC04usestheA2andA1inputsforhard wireaddressingandatotaloffour4Kdevicesmay beaddressedonasinglebussystem.TheA0pinis notconnected.(Thedeviceaddressingisdiscussed indetailundertheDeviceAddressingsection).The codefortheselecteddeviceissetupbyconnecting theseinputstoeitherVSSorVCC.IfA1,A2pins areleftunconnectedinafloatingstatewillbe internallyreadashavingalowinput,VSS,value. • Writeprotect–WP The HT24LC04 has a write protect pin that provides hardwaredataprotection.Thewrite protectpinallowsnormalread/writeoperations whenconnectedtoVSSorleftfloating.Whenthe writeprotectpinisconnectedtoVCC,thewrite protectionfeatureisenabledandoperatesasshown inthefollowingtable. WP Pin Status Protect Array VCC Full Array (4K) VSS or floating Normal Read/Write Operations Memory Organization • HT24LC04,4KSerialEEPROM Internallyorganizedwith5128-bitwords,random wordaddressingrequiresa9-bitdatawordaddress. Device Operations • Clockanddatatransition Datatransfermaybeinitiatedonlywhenthebusis notbusy.Duringdatatransfer,thedatalinemust remainstablewhenevertheclocklineishigh. Changesindatalinewhiletheclocklineishigh willbeinterpretedasaSTARTorSTOPcondition. • Startcondition Ahigh-to-lowtransitionofSDAwithSCLhigh isastartconditionwhichmustprecedeanyother command (refer to Start and Stop Definition Timingdiagram). • Stopcondition Alow-to-hightransitionofSDAwithSCLhighis astopcondition.Afterareadsequence,thestop commandwillplacetheEEPROMinastandby powermode(refertoStartandStopDefinition TimingDiagram). • Acknowledge All addresses and data words are serially transmittedtoandfromtheEEPROMin8-bit words.TheEEPROMsendsazerotoacknowledge thatithasreceivedeachword.Thishappensduring theninthclockcycle. SC L SD A Da ta a ll ow ed to c hange A ddr e ss or a ck now l edge va li d St op co nd it io n St ar t c ondi ti on No A CK st at e Device Addressing The4KEEPROMdevicesrequirean8-bitdevice addresswordfollowingastartconditiontoenablethe chipforareadorwriteoperation.Thedeviceaddress wordconsistofamandatoryone,zerosequencefor thefirstfourmostsignificantbits(refertothediagram showingtheDeviceAddress).Thisiscommontoall theEEPROMdevice. ThenextthreebitsaretheA2,A1andA0device addressbitsforthe1K/2KEEPROM.Thesethreebits mustcomparetotheircorrespondinghardwiredinput pins. The4KEEPROMonlyusetheA2andA1device addressbitswiththethirdbitasamemorypage addressbit.Thetwodeviceaddressbitsmustcompare totheircorrespondinghardwiredinputpins.TheA0 pinisnotconnected. The 8th bit of device address is the read/write operationselectbit.Areadoperationisinitiatedifthis bitishighandawriteoperationisinitiatedifthisbit islow. Ifthecomparisonofthedeviceaddresssucceedthe EEPROMwilloutputazeroatACKbit.Ifnot,the chipwillreturntoastandbystate. R/ W 10 A2 A1 A0 De vi ce A ddr es s 10 |
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