WM8737 datasheet(11/40 Pages) CIRRUS

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Production Data

WM8737L

PD, Rev 4.4, January 2012

SIGNAL TIMING REQUIREMENTS

SYSTEM CLOCK TIMING

MCLK

MCLKL

MCLKH

MCLKY

Figure 1 System Clock Timing Requirements

Test Conditions

DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25

oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

System Clock Timing Information

MCLK System clock pulse width high

TMCLKL

MCLK System clock pulse width low

TMCLKH

MCLK System clock cycle time

TMCLKY

AUDIO INTERFACE TIMING – MASTER MODE

BCLK

(Output)

ADCDAT

ADCLRC

(Output)

DDA

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25

oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless

otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

ADCLRC propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

AUDIO INTERFACE TIMING – SLAVE MODE

BCLK

ADCLRC

BCH

BCL

BCY

ADCDAT

LRSU

LRH

Figure 3 Digital Audio Data Timing – Slave Mode

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