DS868PP2

Copyright 2008 Cirrus Logic, Inc.

7

CS49DV8C Data Sheet

32-bit Audio DSP Family

2.1 Licensing

Licenses are required for Dolby Volume and for all of the third party audio processing algorithms. Please

contact your local Cirrus Sales representative for more information.

3. Firmware Supported

The suite of software available for the CS49DV8C family consists of operating systems (OS) and a

library of overlays. The overlays have been divided into three main groups called Decoders, Mid-

processors, and Post-processors. All software components are defined as follows:

• OS/Kernel - Encompasses all non-audio processing tasks, including loading data from external

memory, processing host messages, calling audio-processing subroutines, auto-detection, error

concealment, etc.

• Dolby Volume - The CS49DV8C can run Dolby Volume on either DSP A or DSP B. On the DSP that

is not running Dolby Volume, it can run the firmware currently available on the CS4953xx family for

that DSP (A or B).

4. Hardware Functional Description

4.1 DSP Core

The CS49DV8C is a dual-core DSP with separate X and Y data and P code memory spaces. Each core

is a high-performance, 32-bit, user-programmable, fixed-point DSP that is capable of performing two

memory access control (MAC) operations per clock cycle. Each core has eight 72-bit accumulators, four

X- and four Y-data registers, and 12 index registers.

Both DSP cores are coupled to a flexible DMA engine. The DMA engine can move data between

peripherals such as the digital audio input (DAI) and digital audio output (DAO), external memory, or any

DSP core memory, all without the intervention of the DSP. The DMA engine offloads data move

instructions from the DSP core, leaving more MIPS available for signal processing instructions.

CS49DV8C functionality is controlled by application codes that are stored in on-board ROM or

downloaded to the CS49DV8C from a host MCU or external FLASH/EEPROM. Users can choose to use

standard audio post-processor modules which are available from Cirrus Logic.

4.1.1 DSP Memory

The memory maps for the DSPs are as follows. All memory sizes are composed of 32-bit words.

4.1.2 DMA Controller

The powerful 12-channel DMA controller can move data between 8 on-chip resources. Each resource

has its own arbiter: X, Y, and P RAM/ROMs on DSP A; X, Y, and P RAM/ROMs on DSP B; external

Table 3. CS49DV8C DSP Memory Sizes

Memory

Type

DSP A

DSP B

X

16k SRAM, 32k ROM

10k SRAM, 8k ROM

Y

24k SRAM, 32k ROM

16k SRAM, 16k ROM

P

8k SRAM, 32k ROM

8k SRAM, 24k ROM