7

DS1072PP1

CS7250B

3 Characteristics and Specifications

Table 3-5. Audio Interface Timing

The

following timing information is valid across the full range of recommended operating conditions.

1.Digital microphone interface timing.

Symbol

Min

Typ

Max

Units

CLK cycle time

313

—

3333

ns

CLK duty cycle

—

60:40

—

40:60

—

CLK rise/fall time

—

—

—

6

ns

DATA enable time

From rising CLK edge, LRSEL = 0

From falling CLK edge, LRSEL = 1

14

14

—

—

—

—

ns

ns

DATA valid time

From rising CLK edge, LRSEL = 0

From falling CLK edge, LRSEL = 1

20

20

—

—

90

90

ns

ns

DATA disable time

From falling CLK edge, LRSEL = 0

From rising CLK edge, LRSEL = 1

—

—

—

—

10

10

ns

ns

Notes:

• The DATA output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected together with

the data from one microphone interleaved with the data from the other. (The microphones must be configured to transmit on opposite

channels in this case.)

• In a typical configuration, the left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the left channel should be

sampled by the receiving device on the falling CLK edge.

• Similarly, the right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the right channel should be

sampled by the receiving device on the rising CLK edge.

• The CS7250B operating mode is selected according to the CLK frequency; see Table 3-4 for further details.

CLK

(input)

DATA is high-impedance (Hi-Z) when not outputting data

DATA

(LRSEL = 1)

DATA

(LRSEL = 0)