84314AY

www.icst.com/products/hiperclocks.html

REV. C JANUARY 27, 2005

2

Integrated

Circuit

Systems, Inc.

ICS84314

nP_LOAD input is initially LOW. The data on inputs M0 through

M8 is passed directly to the M divider. On the LOW-to-HIGH tran-

sition of the nP_LOAD input, the data is latched and the M divider

remains loaded until the next LOW transition on nP_LOAD or until

a serial event occurs. As a result, the M bits can be hardwired to

set the M divider to a specific default state that will automatically

occur during power-up. In parallel mode, the N output divider is

set to 2. In serial mode, the N output divider can be set for either

÷2 or ÷4. The relationship between the VCO frequency, the crys-

tal frequency and the M divider is defined as follows:

The M value and the required values of M0 through M8 are shown

in Table 3B, Programmable VCO Frequency Function Table. Valid

M values for which the PLL will achieve lock for a 16MHz refer-

ence are defined as 125

≤ M ≤ 350. The frequency out

is defined as follows:

Serial operation occurs when nP_LOAD is HIGH and S_LOAD

is LOW. The shift register is loaded by sampling the S_DATA bits

with the rising edge of S_CLOCK. The contents of the shift regis-

ter are loaded into the M divider and N output divider when

S_LOAD transitions from LOW-to-HIGH. The M divide and N out-

put divide values are latched on the HIGH-to-LOW transition of

S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is

passed directly to the M divider and N output divider on each

rising edge of S_CLOCK.

NOTE: The functional description that follows describes

operation using a 16MHz crystal. Valid PLL loop divider

values for different crystal or input frequencies are defined

in the Input Frequency Characteristics, Table 5, NOTE 1.

The ICS84314 features a fully integrated PLL and there-

fore requires no external components for setting the loop

bandwidth. A parallel-resonant, fundamental crystal is used

as the input to the on-chip oscillator. The output of the os-

cillator is divided by 16 prior to the phase detector. With a

16MHz crystal, this provides a 1MHz reference frequency.

The VCO of the PLL operates over a range of 250MHz to

700MHz. The output of the M divider is also applied to the

phase detector.

The phase detector and the M divider force the VCO output

frequency to be 2M times the reference frequency by ad-

justing the VCO control voltage. Note that for some values

of M (either too high or too low), the PLL will not achieve

lock. The output of the VCO is scaled by a divider prior to

being sent to each of the LVPECL output buffers. The divider

provides a 50% output duty cycle.

The programmable features of the ICS84314 support two

input modes to program the M divider. The two input op-

erational modes are parallel and serial.

Figure 1 shows

the timing diagram for each mode. In parallel mode, the

16

fVCO =

fxtal x 2M

S_CLOCK

S_DATA

S_LOAD

nP_LOAD

M0:M8

nP_LOAD

Time

M

t

S

t

H

t

S

t

H

t

S

*NULL *NULL *NULL *NULL

**N

M8M7

M6M5

M4M3

M2M1

M0

*NOTE: The NULL timing slot must be observed.

**NOTE: “N” can only be controlled through serial loading.

fout = fVCO

=

16

2M

fxtal x

N

1

x

N

1

x

e

u

l

a

V

c

i

g

o

L

Ne

d

i

v

i

D

t

u

p

t

u

O

0

÷2

1

÷4