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DAC38RF80IAAVR Datasheet(PDF) 81 Page - Texas Instruments |
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DAC38RF80IAAVR Datasheet(HTML) 81 Page - Texas Instruments |
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81 / 155 page  81 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 www.ti.com SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated Register Maps (continued) Table 42. Register Summary (continued) Address Reset Acronym Register Name Section 0x0B 0x0022 SLEEP_CONFIG Sleep Configuration 8.5.70 0x0C 0xA002 CLK_OUT Divided Output Clock Configuration 8.5.71 0x0D 0xF000 DACFS DAC Fullscale Current 8.5.72 0x0E-0x0F 0x0000 Reserved Reserved 0x10 0x0000 LCMGEN Internal sysref generator 8.5.73 0x11 0x0000 LCMGEN_DIV Counter for internal sysref generator 8.5.74 0x12 0x0000 LCMGEN_SPISYSREF SPI SYSREF for internal sysref generator 8.5.75 0x13-0x1A 0x0000 Reserved Reserved 0x1B 0x0000 DTEST Digital Test Signals 8.5.76 0x1C-0x22 0x0000 Reserved Reserved 0x23 0x03F3 SLEEP_CNTL Sleep Pin Control 8.5.77 0x24 0x1000 SYSR_CAPTURE SYSREF Capture Circuit Control 8.5.78 0x25-0x30 0x0000 Reserved Reserved 0x31 0x0200 CLK_PLL_CFG Clock Input and PLL Configuration 8.5.79 0x32 0x0308 PLL_CONFIG1 PLL Configuration 1 8.5.80 0x33 0x4018 PLL_CONFIG2 PLL Configuration 2 8.5.81 0x34 0x0000 LVDS_CONFIG LVDS Output Configuration 8.5.82 0x35 0x0018 PLL_FDIV Fuse farm clock divider 8.5.83 0x36-0x3A 0x0000 Reserved Reserved 0x3B 0x0002 SRDS_CLK_CFG Serdes Clock Configuration 8.5.84 0x3C 0x8228 SRDS_PLL_CFG Serdes PLL Configuration 8.5.85 0x3D 0x0088 SRDS_CFG1 Serdes Configuration 1 8.5.86 0x3E 0x0909 SRDS_CFG2 Serdes Configuration 2 8.5.87 0x3F 0x0000 SRDS_POL Serdes Polarity Control 8.5.88 0x40-0x75 0x0000 Reserved Reserved 0x76 0x0000 SYNCBOUT JESD204B SYNCB Output 8.5.89 |
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