RT5035B datasheet(39/44 Pages) RICHTEK

39 / 44 page

RT5035A/B

is a registered trademark of Richtek Technology Corporation.

DS5035A/B-02

February

2017

www.richtek.com

Thermal Considerations

For continuous operation, do not exceed absolute

maximum junction temperature. The maximum power

dissipation depends on the thermal resistance of the IC

package, PCB layout, rate of surrounding airflow, and

difference between junction and ambient temperature.

The maximum power dissipation can be calculated by

the following formula :

PD(MAX) = (TJ(MAX)  TA) / JA

where TJ(MAX) is the maximum junction temperature,

TA is the ambient temperature, and JA is the junction to

ambient thermal resistance.

For recommended operating condition specifications,

the maximum junction temperature is 125

C. The

junction to ambient thermal resistance,

JA, is layout

dependent. For WQFN-40L 5x5 package, the thermal

resistance,

JA, is 27.5C/W on a standard JEDEC

51-7 four-layer thermal test board. The maximum

power dissipation at TA = 25C can be calculated by

the following formula :

PD(MAX) = (125C  25C) / (27.5C/W) = 3.63W for

WQFN-40L 5x5 package

The maximum power dissipation depends on the

operating ambient temperature for fixed TJ(MAX) and

thermal resistance,

JA. The derating curve in Figure 1

allows the designer to see the effect of rising ambient

temperature on the maximum power dissipation.

Figure 1. Derating Curve of Maximum Power

Dissipation

Layout Considerations

The PCB layout is an important step to maintain the

high performance of the RT5035A/B. Both the high

current and the fast switching nodes demand full

attention to the PCB layout to save the robustness of

the RT5035A/B through the PCB layout. Improper

layout might show the symptoms of poor line or load

regulation, ground and output voltage shifts, stability

issues,

unsatisfying

EMI

behavior

worsened

efficiency. For the best performance of the RT5035A/B,

the following PCB layout guidelines must be strictly

followed.



Place the input and output capacitors as close as

possible to the input and output pins respectively for

good filtering.



Keep the main power traces as wide and short as

possible.



The switching node area connected to LX and

inductor should be minimized for lower EMI.



Place the feedback components as close as possible

to the FB pin and keep these components away from

the noisy devices.



Connect the GND and Exposed Pad to a strong

ground plane for maximum thermal dissipation and

noise protection.



Directly connect

the output

capacitors to the

feedback network of each channel to avoid bouncing

caused by parasitic resistance and inductance from

the PCB trace.



For the 32-kHz oscillator to the best performance,

observe the following guidelines :



Place the crystal and its components close to the

oscillator side and the oscillator pins.



Ensure that the ground plane under the oscillator and

its components are of good quality.



Avoid placing a separate ground under the oscillator

and connecting it to the general ground through a

single point.



Avoid long connections to the crystal and to the load

capacitor that create a large loop on the PCB.



Use a short connection between the two crystal load

capacitors and route the common connection to the

oscillator ground reference.

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

100

125

Ambient Temperature (°C)

Four-Layer PCB

RT5035B Datasheet(PDF) 39 Page - Richtek Technology Corporation

RT5035B Datasheet(HTML) 39 Page - Richtek Technology Corporation

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