 2004 Microchip Technology Inc.

DS21191M-page 1

24AA128/24LC128/24FC128

Device Selection Table

Features

• Low-power CMOS technology:

- Maximum write current 3 mA at 5.5V

- Maximum read current 400

µA at 5.5V

- Standby current 100 nA typical at 5.5V

• Cascadable for up to eight devices

• Self-timed erase/write cycle

• 64-byte Page Write mode available

• 5 ms max write cycle time

• Hardware write-protect for entire array

• Output slope control to eliminate ground bounce

• Schmitt Trigger inputs for noise suppression

• 1,000,000 erase/write cycles

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP, SOIC, TSSOP, MSOP and DFN

packages, 14-lead TSSOP package

• Standard and Pb-free finishes available

• Temperature ranges:

Description

The Microchip Technology Inc. 24AA128/24LC128/

24FC128 (24XX128*) is a 16K x 8 (128 Kbit) Serial

Electrically Erasable PROM (EEPROM), capable of

operation across a broad voltage range (1.8V to 5.5V).

It has been developed for advanced, low-power

applications such as personal communications or data

acquisition. This device also has a page write capabil-

ity of up to 64 bytes of data. This device is capable of

both random and sequential reads up to the 128K

boundary. Functional address lines allow up to eight

devices on the same bus, for up to 1 Mbit address

space. This device is available in the standard 8-pin

plastic DIP, SOIC (150 and 208 mil), TSSOP, MSOP,

DFN and 14-lead TSSOP packages.

Block Diagram

Package Types

*24XX128 is used in this document as a generic part number for the 24AA128/24LC128/24FC128 devices.

Part

Number

Range

Max. Clock

Frequency

Temp.

Ranges

24AA128

1.8-5.5V

I

24LC128

2.5-5.5V

400 kHz

I, E

24FC128

1.8-5.5V

I

Note 1:

2:

- Industrial (I):

-40

°C to +85°C

- Automotive (E):

-40

°C to +125°C

HV Generator

EEPROM

Array

Page Latches

YDEC

XDEC

Sense Amp.

R/W Control

M

emory

C

ontrol

L

ogic

I/O

C

ontrol

L

ogic

I/O

A0 A1 A2

SDA

SCL

WP

A0

A1

A2

WP

SCL

SDA

1

2

3

4

8

7

6

5

PDIP/SOIC

TSSOP/MSOP *

A0

A1

A2

1

2

3

4

8

7

6

5

WP

SCL

SDA

TSSOP

DFN

A0

A1

A2

WP

SCL

SDA

5

6

7

8

4

3

2

1

NC

A0

A1

NC

A2

NC

NC

WP

NC

SCL

SDA

NC

1

2

3

4

14

13

12

11

5

10

6

9

7

8

Note: * Pins A0 and A1 are no-connects for the MSOP package only.