68HC908RF datasheet(29/188 Pages) MOTOROLA

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Memory

FLASH 2TS Memory

MC68HC908RF2 — Rev. 4.0

Data Sheet

MOTOROLA

Memory

Program and erase operations are facilitated through control bits in a memory

mapped register. Details for these operations appear later in this section. Memory

in the FLASH 2TS array is organized into pages within rows. For the 2-Kbyte array

on the MC68HC908RF2, the page size is one byte. There are eight pages (or eight

bytes) per row. Programming operations are performed on a page basis, one byte

at a time. Erase operations are performed on a block basis. The minimum block

size is one row of eight bytes. Refer to Table 2-3 for additional block size options.

NOTE:

Sometimes a program disturb condition, in which case an erased bit on the row

being programmed unintentionally becomes programmed, occurs. The embedded

smart programming algorithm implements a margin read technique to avoid

program disturb. The margin read step of the smart programming algorithm is used

to ensure programmed bits are programmed to sufficient margin for data retention

over the device’s lifetime. In the application code, perform an erase operation after

eight program operations (on the same row) to further avoid program disturb.

For availability of programming tools and more information, contact a local

Motorola representative.

NOTE:

A security feature prevents viewing of the FLASH 2TS contents.(1)

2.5.1 FLASH 2TS Control Register

The FLASH 2TS control register (FLCR) controls program, erase, and margin read

operations.

FDIV0 — Frequency Divide Control Bit

This read/write bit selects the factor by which the charge pump clock is divided

from the system clock. See 2.5.2 FLASH 2TS Charge Pump Frequency

Control.

BLK1 — Block Erase Control Bit

This read/write bit together with BLK0 allows erasing of blocks of varying size.

See 2.5.3 FLASH 2TS Erase Operation for a description of available block

sizes.

1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or

copying the FLASH 2TS difficult for unauthorized users.

Address:

$FE08

Bit 7

654321

Bit 0

Read:

FDIV0

BLK1

BLK0

HVEN

MARGIN

ERASE

PGM

Write:

Reset:

00000000

= Unimplemented

Figure 2-3. FLASH 2TS Control Register (FLCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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