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ADC32RF82IRMPR Datasheet(PDF) 35 Page - Texas Instruments |
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ADC32RF82IRMPR Datasheet(HTML) 35 Page - Texas Instruments |
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35 / 151 page ![]() IQ 3 GSPS N/2 ADC NCO 2, 16 Bits 3 GSPS IQ data, 3 GSPS RX1 IQ Output GPIO SYSREF RX2 IQ Output NCO 1, 16 Bits NCO 3, 16 Bits NCO 4, 16 Bits RX1 Real Output Wideband IQ Output 2,3 Wideband Real Output RX2 Real Output JESD204B fOUT / 4 2 fOUT / 4 fOUT / 4 LPF LPF 2 LPF LPF N/2 2 LPF LPF IQ data Real[ ] Real[ ] Real[ ] IQ data IQ data 35 ADC32RF82 www.ti.com SBAS869 – SEPTEMBER 2017 Product Folder Links: ADC32RF82 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated 8.3.4.1 Operating Mode: Receiver In receiver mode, the DDC block can be configured as shown in Figure 79 to single- or dual-band operation. Both DDC chains use the same decimation filter setting and the available options are discussed in the Decimation Filters section. The decimation filter setting also directly affects the interface rate and number of lanes of the JESD204B interface. NOTE: Red traces show SYSREF going to the NCO blocks. Figure 79. Decimation Filter Option for Single- or Dual-Band Operation |
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