EC8320 datasheet(13/16 Pages) E-CMOS

13 / 16 page

2A Low Dropout Regulator with Enable

EC8320

E-CMOS Corp. (www.ecmos.com.tw)

Page 13 of 16

3G18N-Rev.P001

Function Description(Cont.)

EC8320B: A logic low signal applied to this pin shuts

down the output. Following a shutdown, a logic high

signal re-enables the output through initiation of a new

soft-start cycle. When left open, this pin is pulled up by

an internal current source (5uA typical) to turn off

operation.

Power-OK and Delay

The EC8320 indicates the status of the output voltage by

monitoring the feedback voltage (VADJ) on ADJ pin. As the

VADJ rises and reaches the rising Power-OK voltage

threshold(VTHPOK), an internal delay function starts to

work. At the end of the delay time, the IC turns off the

internal NMOS of the POK to indicate the output is ok. As

the VADJ falls and reaches the falling Power-OK voltage

threshold, the IC turns on the NMOS of the POK ( after a

debounce time of 10ms typical ).

EC8320 Datasheet(PDF) 13 Page - E-CMOS Corporation