89LPC925 datasheet(17/49 Pages) PHILIPS

17 / 49 page

Philips Semiconductors

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 03 — 15 December 2004

17 of 49

9397 750 14471

8.6 CPU Clock (CCLK) wake-up delay

The P89LPC924/925 has an internal wake-up timer that delays the clock until it

stabilizes depending to the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK

cycles plus 60 to 100

µs. If the clock source is either the internal RC oscillator,

watchdog oscillator, or external clock, the delay is 224 OSCCLK cycles plus

60 to 100

µs.

8.7 CPU Clock (CCLK) modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a

dividing register, DIVM, to generate CCLK. This feature makes it possible to

temporarily run the CPU at a lower rate, reducing power consumption. By dividing the

clock, the CPU can retain the ability to respond to events that would not exit Idle

mode by executing its normal program at a lower rate. This can also allow bypassing

the oscillator start-up time in cases where Power-down mode would otherwise be

used. The value of DIVM may be changed by the program at any time without

interrupting code execution.

8.8 Low power select

The P89LPC924/925 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to ‘1’ to lower the

power consumption further. On any reset, CLKLP is ‘0’ allowing highest performance

access. This bit can then be set in software if CCLK is running at 8 MHz or slower.

89LPC925 Datasheet(PDF) 17 Page - NXP Semiconductors