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ST72324BL Datasheet(PDF) 127 Page - STMicroelectronics |
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ST72324BL Datasheet(HTML) 127 Page - STMicroelectronics |
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127 / 151 page  ST72F324L, ST72324BL 127/151 12.9 CONTROL PIN CHARACTERISTICS 12.9.1 Asynchronous RESET Pin Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified. Figure 72. Typical Application with RESET pin 6)7)8) Notes: 1. Data guaranteed by design, not tested in production. 2. Hysteresis voltage between Schmitt trigger switching levels. 3. The IIO current sunk must always respect the absolute maximum rating specified in Section 12.2.2 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on the RESET pin with a duration below th(RSTL)in can be ignored. 5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en- vironments. 6. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset (watchdog). 7. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below the VIL max. level specified in Section 12.9.1 . Otherwise the reset will not be taken into account internally. 8. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure that the current source on the RESET pin (by an external pull-up for example) is less than the absolute maximum value specified for IINJ(RESET) in Section 12.2.2 on page 111. Symbol Parameter Conditions Min Typ Max Unit VIL Input low level voltage 1) Flash versions 0.16xVDD V ROM versions 0.3xVDD VIH Input high level voltage 1) Flash versions 0.85xVDD ROM versions 0.7xVDD Vhys Schmitt trigger voltage hysteresis 2) 2.5 VOL Output low level voltage1) IIO=+2mA 0.3 0.7 V IIO Output current on RESET pin when driven low internally 2mA RON Weak pull-up equivalent resistor VDD=3V 50 82 150 k Ω tw(RSTL)out Generated reset pulse duration Internal reset sources 13 30 721) µs th(RSTL)in External reset pulse hold time 4) 2.5 µs tg(RSTL)in Filtered glitch duration 5) 200 ns 0.01 µF VDD 0.01 µF EXTERNAL RESET CIRCUIT 5) USER VDD 4.7k Ω Required Recommended ST72XXX PULSE GENERATOR Filter RON VDD WATCHDOG RESET INTERNAL RESET 1 |
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