ST72324BL datasheet(15/151 Pages) STMICROELECTRONICS

15 / 151 page

ST72F324L, ST72324BL

15/151

Notes:

1. The contents of the I/O port DR registers are readable only in output configuration. In input configura-

tion, the values of the I/O pins are returned instead of the DR register contents.

2. The bits associated with unavailable pins must always keep their reset value.

3. The Timer A Input Capture 2 pin is not available (not bonded).

– In Flash devices:

The TAIC2HR and TAIC2LR registers are not present. Bit 4 of the TACSR register (ICF2) is forced

by hardware to 0. Consequently, the corresponding interrupt cannot be used.

4. The Timer A Output Compare 2 pin is not available (not bonded).

– In ROM devices:

The TAOC2HR and TAOC2LR Registers can be used in PWM mode or for timebase generation.

– In Flash devices:

The TAOC2HR and TAOC2LR Registers are write only, reading them will return undefined values.

Bit 3 of the TACSR register (OCF2) is forced by hardware to 0. Consequently, the corresponding in-

terrupt cannot be used.

Caution: The TAIC2HR and TAIC2LR registers and the ICF2 and OCF2 flags are not present in the

ST72F324L but are present in the emulator. For compatibility with the emulator, it is recommended to per-

form a dummy access (read or write) to the TAIC2LR and TAOC2LR registers to clear the interrupt flags.

ST72324BL Datasheet(PDF) 15 Page - STMicroelectronics