ST72324BL datasheet(149/151 Pages) STMICROELECTRONICS

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ST72F324L, ST72324BL

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15.1.6 SCI Wrong Break duration

Description

A single break character is sent by setting and re-

setting the SBK bit in the SCICR2 register. In

some cases, the break character may have a long-

er duration than expected:

- 20 bits instead of 10 bits if M=0

- 22 bits instead of 11 bits if M=1.

In the same way, as long as the SBK bit is set,

break characters are sent to the TDO pin. This

may lead to generate one break more than expect-

ed.

Occurrence

The occurrence of the problem is random and pro-

portional to the baudrate. With a transmit frequen-

19200

baud

(fCPU=8MHz

and

SCI-

BRR=0xC9), the wrong break duration occurrence

is around 1%.

Workaround

If this wrong duration is not compliant with the

communication protocol in the application, soft-

ware can request that an Idle line be generated

before the break character. In this case, the break

duration is always correct assuming the applica-

tion is not doing anything between the idle and the

break. This can be ensured by temporarily disa-

bling interrupts.

The exact sequence is:

- Disable interrupts

- Reset and Set TE (IDLE request)

- Set and Reset SBK (Break Request)

- Re-enable interrupts

15.2 ROM DEVICES ONLY

15.2.1 I/O Port A and F Configuration

When using an external quartz crystal or ceramic

resonator, the fOSC2 clock may be disturbed be-

cause the device goes into reserved mode control-

led by Port A and F.

This happens with either one of the following con-

figurations:

PA3=0, PF4=1, PF1=0 when the PLL option is dis-

abled and PF0 is toggling

PA3=0, PF4=1, PF1=0, PF0=1 when the PLL op-

tion is enabled

This is detailed in the following table:

As a consequence, for cycle-accurate operations,

these configurations are prohibited in either input

or output mode.

Workaround:

To avoid this occurring, it is recommended to con-

nect one of these pins to GND (PF4 or PF0) or

VDD (PA3 or PF1).

15.3 FLASH DEVICES ONLY

15.3.1 Timer A Restrictions in Flash Devices

In Flash devices, Timer A functionality has the fol-

lowing restrictions:

– TAOC2HR and TAOC2LR registers are write

only

– Input Capture 2 is not implemented

– The corresponding interrupts cannot be used

(ICF2, OCF2 forced by hardware to zero)

15.3.2 External clock source with PLL

External clock source is not supported with the

PLL enabled.

15.3.3 39-Pulse ICC Entry Mode

ICC mode entry using ST7 application clock (39

pulses) is not supported. External clock mode

must be used (36 pulses). Refer to the ST7 Flash

Programming Reference Manual.

PLL PA3 PF4 PF1 PF0 Clock Disturbance

OFF

Tog-

gling

Max. 2 clock cycles

lost at each rising or

falling edge of PF0

Max. 1 clock cycle

lost out of every 16

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