TMS320LC2402A datasheet(17/133 Pages) TI

17 / 133 page

TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A

TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A

DSP CONTROLLERS

SPRS145J − JULY 2000 − REVISED NOVEMBER 2004

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

pin functions (continued)

Table 2. LF240xA and LC240xA Pin List and Package Options†‡ (Continued)

PIN NAME

LF2407A

(144-PGE)

2406A

(100-PZ)

LC2404A

(100-PZ)

2403A,

LC2402A

(64-PAG)

and

2402A

(64-PG)

DESCRIPTION

ADDRESS, DATA, AND MEMORY CONTROL SIGNALS (CONTINUED)

I/O space strobe. IS, DS, and PS are always high

unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state.¶

Program space strobe. IS, DS, and PS are always

high unless low-level asserted for access to the

relevant external memory space or I/O. They are

placed in the high-impedance state.¶

R/W

Read/write qualifier signal. R/W indicates transfer

direction during communication to an external

device. It is normally in read mode (high), unless

low level is asserted for performing a write

operation. R/W is placed in the high-impedance

state.¶

W/R / IOPC0

W/R

Write/Read qualifier or GPIO. This is an inverted

R/W signal useful for zero-wait-state memory

interface. It is normally low, unless a memory write

W/R / IOPC0

IOPC0

interface. It is normally low, unless a memory write

operation is performed. See Table 12, Port C

section, for reset note regarding LF2406A and

LF2402A.

(

↑)

Read-enable strobe. Read-select indicates an

active, external read cycle. RD is active on all

external program, data, and I / O reads. RD is

placed in the high-impedance state.¶

Write-enable strobe. The falling edge of WE

indicates that the device is driving the external

data bus (D15 − D0). WE is active on all external

program, data, and I/O writes. WE is placed in the

high-impedance state.¶

STRB

External memory access strobe. STRB is always

high unless asserted low to indicate an external

bus cycle. STRB is active for all off-chip

accesses. STRB is placed in the high-impedance

state.¶

† Bold, italicized pin names indicate pin function after reset.

‡ GPIO − General-purpose input/output pin. All GPIOs come up as input after reset.

§ It is highly recommended that VCCA be isolated from the digital supply voltage (and VSSA from digital ground) to maintain the specified accuracy

and improve the noise immunity of the ADC.

¶ Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high

# No power supply pin (VDD, VDDO, VSS, or VSSO) should be left unconnected. All power supply pins must be connected appropriately for proper

device operation.

LEGEND:

↑ − Internal pullup

↓ − Internal pulldown

(Typical active pullup/pulldown value is

±16 µA.)

TMS320LC2402A Datasheet(PDF) 17 Page - Texas Instruments

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