ADT7301

Rev. B | Page 4 of 16

TIMING CHARACTERISTICS

Table 2.

Parameter1

Limit

Unit

Comments

t

1

5

ns min

CS to SCLK setup time

t

2

25

ns min

SCLK high pulse width

t

3

25

ns min

SCLK low pulse width

t

4

2

35

ns max

Data access time after SCLK falling edge

t

5

20

ns min

Data setup time prior to SCLK rising edge

t

6

5

ns min

Data hold time after SCLK rising edge

t

7

5

ns min

CS to SCLK hold time

t

8

2

40

ns max

CS to DOUT high Impedance

1.6V

200

µA

200

µA

TO

OUTPUT

PIN

50pF

Figure 2. Load Circuit for Data Access Time and Bus Relinquish Time