ADV7202 datasheet(13/29 Pages) AD

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REV. 0

ADV7202

–12–

XTAL0

DOUT [9:0]

SYNC_OUT

Figure 3. SYNC_OUT Output Timing, YCrCb Input

MPU PORT DESCRIPTION

The ADV7202 supports a 2-wire serial (I

2C-compatible)

microprocessor bus driving multiple peripherals. Two inputs,

serial data (SDA) and serial clock (SCL), carry information

between any device connected to the bus. Each slave device is

recognized by a unique address. The ADV7202 has four pos-

sible slave addresses for both read and write operations. These

are unique addresses for each device and are illustrated in

Figure 4. The LSB sets either a read or write operation. Logic

Level “1” corresponds to a read operation, while Logic Level

“0” corresponds to a write operation. A1 is set by setting the

ALSB pin of the ADV7202 to Logic Level “0” or Logic Level

“1.” When ALSB is set to “0,” there is greater input bandwidth

on the I

2C lines, which allows high speed data transfers on this

bus. When ALSB is set to “1,” there is reduced input band-

width on the I

2C lines, which means that pulses of less than

50 ns will not pass into the I

2C internal controller. This mode is

recommended for noisy systems.

DISABLED

1ENABLED

READ/WRITE

CONTROL

SET UP BY

ALSB

ADDRESS

CONTROL

Figure 4. Slave Address

To control the various devices on the bus, the following proto-

col must be followed. First, the master initiates a data transfer by

establishing a Start condition, defined by a high-to-low transition

on SDA while SCL remains high. This indicates that an address/

data stream will follow. All peripherals respond to the Start

condition and shift the next eight bits (7-bit address + R/

W bit).

The bits are transferred from MSB down to LSB. The periph-

eral that recognizes the transmitted address responds by pulling

the data line low during the ninth clock pulse. This is known as

an Acknowledge Bit. All other devices withdraw from the bus at

this point and maintain an idle condition. The idle condition

is where the device monitors the SDA and SCL lines waiting for

the Start condition and the correct transmitted address. The R/

bit determines the direction of the data.

A Logic “0” on the LSB of the first byte means that the master

will write information to the peripheral. A Logic “1” on the LSB

of the first byte means that the master will read information

from the peripheral.

The ADV7202A acts as a standard slave device on the bus. The

data on the SDA pin is eight bits long, supporting the 7-bit

addresses plus the R/

W bit. It interprets the first byte as the

device address and the second byte as the starting subaddress.

The subaddresses auto-increment, allowing data to be written to

or read from the starting subaddress. A data transfer is always

terminated by a Stop condition. The user can access any unique

subaddress register one-by-one, without updating all the registers.

Stop and Start conditions can be detected at any stage during

the data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCL high period, the

user should only issue one Start condition, one Stop condition,

or a single Stop condition followed by a single Start condition. If

an invalid subaddress is issued by the user, the ADV7202 will

not issue an acknowledge and will return to the idle condition. If

in auto-increment mode, the user exceeds the highest subaddress,

the following action will be taken:

1. In read mode, the highest subaddress register contents

will continue to be output until the master device issues a

no-acknowledge. This indicates the end of a read. A

no-acknowledge condition is where the SDA line is not

pulled low on the ninth pulse.

2. In write mode, the data for the invalid byte will not be

loaded into any subaddress register, a no-acknowledge will

be issued by the ADV7202, and the part will return to the

idle condition.

Figure 5 illustrates an example of data transfer for a read

sequence and the Start and Stop conditions.

1–7

START ADDR R/

W ACK SUBADDRESS ACK

DATA

ACK

STOP

SDATA

SCLOCK

Figure 5. Bus Data Transfer

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